參數(shù)資料
型號: MC145170
廠商: Motorola, Inc.
英文描述: PLL Frequency Synthesizer(PLL頻率發(fā)生器)
中文描述: 鎖相環(huán)頻率合成器(PLL頻率發(fā)生器)
文件頁數(shù): 2/14頁
文件大?。?/td> 173K
代理商: MC145170
2
MOTOROLA RF/IF APPLICATIONS INFORMATION
To simulate the operation of the PLL loop, we need only a
model for the phase detector, a model for the VCO and the
loop filter. The reference frequency is the frequency of the
oscillator divided by the value programmed into the R
counter. Rather than overloading the circuit simulation with a
higher frequency followed by a counter, the reference
frequency is used directly. In the same manner, the input
amplifier and N counter can be folded into the model for the
VCO.
Phase Detector Model
Figure 2 shows the input and output signals for the
MC145170 phase detector. To accurately simulate the
operation of the phase detector, it is necessary for the model
to duplicate the output signals shown for the given input
signals. PhiR produces an output pulse when the reference
signal leads the signal from the VCO with a pulse width equal
to the amount of lead. PhiV produces the reverse condition
and results from the reference signal lagging the feedback
from the VCO. PDout is the summation of PhiR and PhiV with
the PhiR component driving positive and PhiV driving
negative and high impedance between pulses. LD is also a
summation but without the high impedance state. When
either PhiR or PhiV is representing a non–zero lead or lag,
the other will generate a pulse of minimum width. Both
outputs will generate a minimum width pulse when locked.
The minimum width of the output pulse is specified in the
MC145170 data sheet and is 50 ns typical.
NOTE:
The PDout generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance and
the voltage at that pin is determined by the low–pass filter capacitor. PDout,
φ
R, and
φ
V are shown with the polarity bit (POL) = low;
see Figure 14 for POL.
fR
Reference
OSCin
÷
R
fV
Feedback
(fin
÷
N)
PDout
φ
R
φ
V
LD
VH
VL
VH
VH
VL
VH
VL
High Impedance
VH
VL
VH
VL
VL
VH = High voltage level
VL = Low voltage level
*At this point, when both fR and fV are in phase, both the sinking and sourcing output FETs are turned on for a very short interval.
*
Figure 2.
The block diagram for a model for the phase detector is
shown in Figure 3. Two pulse generators produce narrow
pulses coincident with the leading edges of In and Ref. The
pulse generated from Ref is compared with In to determine if
it leads or lags and the pulse generated from In is compared
with Ref. These signals drive the RS flip–flops which
generate the basic correction signals. Since the model would
generate no output when the circuit is locked, the NOR gates
are added so the pulses are present in the output.
Figure 3.
HB1
Pulse Generator
Pulse Generator
HB2
HB6
HB5
HB3
HB4
2
Comparator
2
Comparator
1
Ref
In
RSFF
phiV
phiR
U4
3
nor2
2
1
U3
3
nor2
2
1
RSFF
2
1
2
1
1
O
O
O
O
O
O
1
1
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參數(shù)描述
MC145170D1 制造商: 功能描述: 制造商:Motorola Inc 功能描述: 制造商:undefined 功能描述:
MC145170D2 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MC145170D2R2 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MC145170DT2 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MC145170DT2R2 功能描述:IC SERIAL PLL FREQ SYNTH 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*