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| 型號(hào)： | MB86967PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| 中文描述： | 1 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁(yè)數(shù)： | 6/129頁(yè) |
| 文件大小： | 1499K |
| 代理商： | MB86967PFV |
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6
MB86967
I
PIN DESCRIPTION
System interface pins in PC card mode
(Continued)
Pin no.
18 to 23,
25,
27 to 29,
85,
87 to 91
4 to 14
Symbol
PD0 to PD15
Pin name
I/O
BD
Function
PC CARD DATA BUS
PD15 for most significant bit and PD0 for least
significant bit. A built-in 150-k
pull-down resistor
eliminates the need for any resistor on the card.
PA0 to PA10
PC CARD ADDRESS
BUS
ID
PA10 for most significant bit and PA0 for least
significant bit. PA0 is invalid at word access. A built-in
150-k
pull-down resistor eliminates the need for any
resistor on the card.
CE1 controls even addresses and CE2 controls odd
addresses. At power-on or after reset-canceling,
these pins must be kept High for 20 ms to initialize
the I/O card.
This pin is used to control the output of read data
from attribute memory space.
This pin is used to control a write operation to
attribute memory space.
This pin must be kept Non-active High at access to
common memory. Keeping this pin Low accesses
attribute memory by OE/WE. The I/O area is
accessed by IORD/IOWE. Attribute memory is
allocated only to even addresses. Therefore, for word
access, data signals PD0 to PD7 are valid and PD8
to PD15 are invalid. Access to odd addresses is
disabled at byte access. When setting IORD/IOWE
Low during DMA operation, REG must be kept High
to prevent illegal access.
ISU This pin is used to clear the card configuration
register (CCR), set the card to an unset state (IC
card interface mode), and initialize the pointers and
registers in the LAN controller and 10BASE-T
transceiver. When power is applied to the card, the
system must keep this pin High or high-impedance
for 1 ms after the power supply has stabilized. A built-
in 150-k
pull-down resistor eliminates the need for
any resistor on the card.
ISD This pin is internally ORed with RESET1 and
contains a 50-k
pull-down resistor.
IU
This pin is used to read data from the I/O area. The
MB86967 sends no response to IORD until a write
operation to the CCR sets the card to the I/O card
interface mode.
IU
This pin is used to write data to the I/O area. The
MB86967 sends no response to IOWR until a write
operation to the CCR sets the card to the I/O card
interface mode.
O
A Low level is output to this pin to delay the end of an
I/O access cycle in progress.
82
83
CE1
CE2
CARD ENABLE 1,2
IU
96
OE
OUTPUT ENABLE
IU
95
WE
WRITE ENABLE
IU
93
REG
REGISTER SELECT
IU
64
RESET1
HARDWARE RESET1
(Active High)
63
RESET2
HARDWARE RESET2
(Active High)
I/O READ
15
IORD
17
IOWR
I/O WRITE
3
WAIT
WAIT
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