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36
MB86967
2. Explanation of Control Registers in LAN Controller
2.1 Data Link Controller Register
(1) DLCR0: Transmit Status Register
DLCR0 indicates the transmit status of the data link controller. The external interrupt INT is asserted by setting
the bits of DLCR2 corresponding to the status bits, bit 7 and bit 3 to 0.
(Continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BUS WR
ERR
BIT CLR
0
Read
TMT OK
NET BSY TMT REC SRT RKT
JABBER
COL
16 COL
Write
BIT CLR
0
—
—
0
—
0
BIT CLR
0
BIT CLR
0
BIT CLR
0
Initial Value
Undefined
Bit no.
7
Bit name
TMT OK
(Transmit O.K)
Operation
Read
Value
0
1
Function
Indicates transmission in progress
This bit is set automatically when transmission of all packets
in the transmitter buffer is completed. In the single buffer
mode, the next transmit data can be transferred from the host
system. In the dual buffer mode, transmission of data from
the second bank can be started (Bit 7 (TMST) of the BMR10
is set). The dual buffer mode permits transfer of the next
transmit data from the host system to one buffer, while the
other buffer is transmitting packets.
Not affected
This bit is cleared.
Indicates network empty (no carrier detected)
Indicates network in use (carrier detected)
Not affected
Indicates packets transmitted by this register not received
normally.
This bit is cleared automatically at the start of transmission of
each packet.
Indicates packets transmitted by this register received
normally.
This bit must not be used in normal operation.
Not affected
No short packet error.
This bit is cleared automatically at the start of transmission of
each packet.
Indicates network carrier detect disappeared during packet
transmission.
This bit is usually set in the event of a packet collision or
physical damage to the cable.
Not affected
Write
0
1
0
1
—
0
6
NET BSY
(Net Busy)
Read
Write
Read
5
TMT REC
(Transmit
Packet Receive)
1
Write
Read
—
0
4
SRT PKT
(Short Packet)
1
Write
—