參數(shù)資料
型號(hào): MB86967PFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
中文描述: 1 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80
封裝: PLASTIC, LQFP-80
文件頁數(shù): 41/129頁
文件大小: 1499K
代理商: MB86967PFV
41
MB86967
(4) DLCR3: Receive Interrupt Enable Register
The DLCR3 register enables a receive interrupt. When the bit corresponding to the status bit of DLCR1 is set
to 1, the external interrupt INT is asserted when the status bit is set.
Bit 7
ENA PKT
RDY
0
Bit 6
Bit 5
Bit 4
ENA
RMT RST
0
Bit 3
ENA RX
SRT PKT
0
Bit 2
Bit 1
ENA
Bit 0
ENA
OVRFLO
0
Read/Write
ENA BUS
RD ERR
0
ENA DMA
EOP
0
ENA ALG
ERR
0
CRC ERR
0
Initial Value
Bit no.
7
Bit name
ENA PKT RDY
Operation
Read/Write
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Disables PKT RDY interrupt
Enables TMT OK interrupt
Disables BUS RD ERR interrupt
Enables BUS RD ERR interrupt
Disables DMA EOP interrupt
Enables DMA EOP interrupt
Disables RMT RST interrupt
Enables RMT RST interrupt
Disables RX SRT ERR interrupt
Enables RX SRT ERR interrupt
Disables ALG ERR interrupt
Enables ALG ERR interrupt
Disables CRC ERR interrupt
Enables CRC ERR interrupt
Disables OVRFLO interrupt
Enables OVRFLO interrupt
6
ENA BUS RD
ERR
Read/Write
5
ENA DMA EOP Read/Write
* :This bit is invalid in the
PC card mode.
4
ENA RMT RST
Read/Write
3
ENA RX SRT
ERR
Read/Write
2
ENA ALG ERR
Read/Write
1
ENA CRC ERR Read/Write
0
ENA OVRFLO
Read/Write
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