- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377895 > MB86967PFV (FUJITSU LTD) LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces PDF資料下載
參數(shù)資料
| 型號： | MB86967PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| 中文描述： | 1 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 51/129頁 |
| 文件大?。?/td> | 1499K |
| 代理商： | MB86967PFV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當(dāng)前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁
51
MB86967
(4) BMPR12: DAM Enable Register
The BMPR12 controls DMA transfer between the host system and the MB86967.
*1: The DLCR1 DMAEOP bit is cleared if the DMA RENA bit and DMA TENA bit are set to “00”.
*2: Writing “11” to both DMA RENA bit and DMA TENA bit is prohibited.
Bit 7
×
0
Bit 6
×
0
Bit 5
×
0
Bit 4
×
0
Bit 3
Bit 2
Bit 1
Bit 0
Read
Write
Initial
Value
LONGPKT
RCV DIS
0
DMA
RENA
DMA
TENA
×
×
×
×
0
0
0
0
Bit no.
7 to 4
Bit name
Not used
Operation
Read
Write
Read/Write
Value
—
0
0
Function
The read values of these bits are always undefined.
Writing 1 is prohibited. Always write 0 at writing.
The receive long packet removal function is enabled.
Packets with a length of 1792 bytes or more are not received.
The receive long packet removal function is disabled.
Packets with a length of up to 2047 bytes cannot be received
normally.
The read value of this bit is always 0.
Writing 1 is prohibited. Always write 0 at writing.
DMA read operation is disabled.
DMA read operation (reading from
receiver buffer) is enabled.
The DMA write operation is
disabled.
The DMA write operation (writing to
receiver buffer) is enabled.
3
LONGPKT RCV
DIS
1
2
Not used
Read/Write
—
1
DMA RENA
Read/Write
0 (*1)
1 (*2)
* :Writing 1 to this bit is
prohibited in the PC
card mode. Always
write 0 to this bit.
0
DMA TENA
Read/Write
0 (*1)
1 (*2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86977 | IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | IP PACKET FORWARDING ENGINE |
| MB86H20 | SmartMPEG |
| MB86H21 | MPEG-2 Decoder with Integrated NDS ICAM |
| MB86H22 | MPEG-2 Decoder for ext. Temperature Range |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB86A22PMC-ES-BNDE1 | 制造商:FUJITSU 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。