參數(shù)資料
型號(hào)： MB8118165B-60
廠商： Fujitsu Limited
英文描述： CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 100萬× 16位的超頁模式動(dòng)態(tài)RAM的CMOS（100萬× 16位超級(jí)頁面存取模式動(dòng)態(tài)內(nèi)存）
文件頁數(shù)： 25/28頁
文件大?。?/td> 651K
代理商： MB8118165B-60
25
MB8118165B-50/-60
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function of
CAS-before-RAS refresh circuitry. If a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held Low,
read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
9
are defined by the on-chip refresh counter.
Column Addresses: Bits A
0
through A
9
are defined by latching levels on A
0
to A
9
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows;
1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 1,024 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 1,024 times with addresses generated by the
internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 1,024 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
(At recommended operating conditions unless otherwise noted.)
Fig. 19 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
DQ
(Input)
DQ
(Output)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
LCAS
or
UCAS
WE
A
0
to A
9
V
OH
V
OL
V
IH
V
IL
OE
t
CSR
t
RP
t
RCS
t
FCAH
t
ASC
t
CWL
t
WP
t
CHR
t
FRSH
t
RWL
t
FCWD
t
DH
t
DS
t
DZC
t
OED
t
DZO
t
OEZ
t
OEH
VALID DATA IN
COLUMN ADDRESSES
t
FCAC
HIGH-Z
HIGH-Z
t
FCAS
t
OEA
t
CP
Parameter
Unit
Min.
Max.
ns
No.
Min.
Max.
—
—
50
45
Symbol
35
—
—
ns
35
71
72
73
70
—
—
ns
63
50
—
—
ns
45
50
—
—
ns
45
MB8118165B-50
MB8118165B-60
Access Time from CAS
Column Address Hold Time
CAS to WE Delay Time
CAS Pulse width
RAS Hold Time
70
69
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
t
ON
Note:
Assumes that CAS-before-RAS refresh counter test cycle only.
HIGH-Z
Valid Data
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H
→
L” or “L
→
H” transition (Address and DQ)
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