參數(shù)資料
型號(hào): MB814100A-60
廠商: Fujitsu Limited
英文描述: CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動(dòng)態(tài)RAM)
中文描述: 的CMOS 4米× 1位快速頁面模式的DRAM的CMOS(4分× 1位快速頁面存取模式動(dòng)態(tài)內(nèi)存)
文件頁數(shù): 1/25頁
文件大小: 309K
代理商: MB814100A-60
1
DS05-10142-4E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS 4 M
FAST PAGE MODE DRAM
×
1 BIT
MB814100A-60/-70/-80
CMOS 4,194,304
×
1 bit Fast Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB814100A is a fully decoded CMOS Dynamic RAM (DRAM) that contains a total of 4,194,304
memory cells in a
×
1 configuration. The MB814100A features a ”fast page” mode of operation whereby high-
speed random access of up to 2,048-bits of data within the same row can be selected. The MB814100A DRAM
is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB814100A is very small, the device can be used as a non-volatile memory in equipment
that uses batteries for primary and/or auxiliary power.
The MB814100A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process.
This process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft
errors and extends the time interval between memory refreshes. Clock timing requirements for the MB814100A
are not critical and all inputs are TTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB814100A-60
MB814100A-70
MB814100A-80
RAS Access Time
60 ns max.
70 ns max.
80 ns max.
CAS Access Time
15 ns max.
20 ns max.
20 ns max.
Address Access Time
30 ns max.
35 ns max.
40 ns max.
Randam Cycle Time
110 ns min.
125 ns min.
140 ns min.
Fast Page Mode Cycle Time
40 ns min.
45 ns min.
45 ns min.
Low Power
Dissipation
Operating current
605 mW max.
550 mW max.
495 mW max.
Standby current
11 mW max. (TTL level) / 5.5 mW max. (CMOS level)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
4,194,304 words
×
1 bit organization
Silicon gate, CMOS, 3D-Stacked
Capacitor Cell
All input and output areTTL compatible
1024 refresh cycles every16.4 ms
Common I/O capability by using early write
RAS only, CAS-before-RAS, or Hidden
Refresh
Fast page Mode, Read-Modify-Write
capability
On chip substrate bias generator for high
performance
相關(guān)PDF資料
PDF描述
MB814100A-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動(dòng)態(tài)RAM)
MB814100A-80 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動(dòng)態(tài)RAM)
MB814100C-60 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1 位快速頁面存取模式動(dòng)態(tài)RAM)
MB814100C-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位快速頁面存取模式動(dòng)態(tài)RAM)
MB814100D-60 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動(dòng)態(tài)RAM)
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