參數(shù)資料
型號(hào): MB814100D-60
廠商: Fujitsu Limited
英文描述: CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動(dòng)態(tài)RAM)
中文描述: 的CMOS 4米× 1位快速頁面模式的DRAM(的CMOS 4米× 1位速頁面存取模式動(dòng)態(tài)內(nèi)存)
文件頁數(shù): 1/23頁
文件大?。?/td> 238K
代理商: MB814100D-60
1
DS05-10163-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
COS 4 M
FAST PAGE MODE DYNAMIC RAM
×
1 BIT
MB814100D-60/-70
CMOS 4,194,304
×
1 Bit Fast Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB814100D is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory cells
in 4M
×
1 configuration. The MB814100D features a “fast page” mode of operation whereby high-speed random
access of up to 2,048-bits of data within the same row can be selected. The MB814100D DRAM is ideally suited
for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where
very low power dissipation and wide bandwidth are basic requirements of the design. Since the standby current
of the MB814100D is very small, the device can be used as a non-volatile memory in equipment that uses batteries
for primary and/or auxiliary power.
The MB814100D is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process.
This process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft
errors and extends the time interval between memory refreshes. Clock timing requirements for the MB814100D
are not critical and all inputs are TTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB814100D-60
MB814100D-70
RAS Access Time
60 ns max.
70 ns max.
CAS Access Time
15 ns max.
20 ns max.
Address Access Time
30 ns max.
35 ns max.
Randam Cycle Time
110 ns min.
125 ns min.
Fast Page Mode Cycle Time
40 ns min.
45 ns min.
Low Power
Dissipation
Operating Current
605 mW max.
550 mW max.
Standby Current
11 mW max. (TTL level) / 5.5 mW max. (CMOS level)
4,194,304 words
×
1 Bit organization
Silicon gate, CMOS, 3D-Stacked
capacitor Cell
All input and output are TTL compatible
1024 refresh cycles every 16.4 ms
RAS only, CAS-before-RAS, or Hidden
Refresh
Fast page Mode, Read-Modify-Write
capability
On chip substrate bias generator for high
performance
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
相關(guān)PDF資料
PDF描述
MB814100D-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動(dòng)態(tài)RAM)
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