參數資料
型號: MB814265-70
廠商: Fujitsu Limited
英文描述: CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級頁面存取模式動態(tài)RAM)
中文描述: 的CMOS 256K × 16位的超頁模式動態(tài)RAM的CMOS(256K × 16位超級頁面存取模式動態(tài)內存)
文件頁數: 1/28頁
文件大?。?/td> 364K
代理商: MB814265-70
1
DS05-10180-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS 256K
HYPER PAGE MODE DYNAMIC RAM
×
16 BIT
MB814265-60/-70
CMOS 262,144
×
16 BIT Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB814265 is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory cells
accessible in 16-bit increments. The MB814265 features the “hyper page” mode of operation which provides
extended valid time for data output and higher speed random access of up to 512
same row than the fast page mode. The MB814265-60/-70 DRAMs are ideally suited for memory applications
such as embedded control, buffer, portable computers, and video imaging equipment where very low power
dissipation and high bandwidth are basic requirements of the design.
×
16-bits of data within the
The MB814265 is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process. This
process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors
and extends the time interval between memory refreshes.
I
PRODUCT LINE & FEATURES
Parameter
MB814265-60
60 ns max.
20 ns max.
30 ns max.
104 ns max.
25 ns min.
523 mW max.
11 mW max. (TTL level)/5.5 mW max. (CMOS level)
MB814265-70
70 ns max.
20 ns max.
35 ns max.
119 ns min.
30 ns min.
462 mW max.
RAS Access Time
CAS Access Time
Address Access Time
Random Cycle Time
Hyper Page Mode Cycle Time
Low Power Dissipation
Operating current
Standby current
262,144 words
×
16 bit organization
Silicon gate, CMOS, Advanced Stacked
Capacitor Cell
All input and output are TTL compatible
512 refresh cycles every 8.2 ms
9 rows
×
9 columns, addressing scheme
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
Early Write or OE controlled Write capability
RAS-only, CAS-before-RAS, or Hidden Refresh
Hyper page mode, Read-Modify-Write capability
On chip substrate bias generator for high
performance
相關PDF資料
PDF描述
MB814400A-60 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動態(tài)RAM)
MB814400A-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動態(tài)RAM)
MB814400A-80 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動態(tài)RAM)
MB814400C-60 CMOS 1 M ×4BIT Fast Page Mode DRAM(CMOS 1 M ×4 位快速頁面存取模式動態(tài)RAM)
MB814400C-70 CMOS 1 M ×4 BIT Fast Page Mode DRAM(CMOS 1 M ×4 位快速頁面存取模式動態(tài)RAM)
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