參數(shù)資料
型號(hào)： MB814100D-60
廠商： Fujitsu Limited
英文描述： CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 1位快速頁(yè)面模式的DRAM（的CMOS 4米× 1位速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 9/23頁(yè)
文件大?。?/td> 238K
代理商： MB814100D-60
9
MB814100D-60/MB814100D-70
Notes: 1.
Referenced to V
SS
.
I
CC
depends on the output load conditions and cycle rates; The specified values are obtained with the
output open.
I
CC
depends on the number of address change as RAS = V
IL
and CAS = V
IH
, V
IL
> –0.5 V. I
CC1
, I
CC3
and
I
CC5
are specified at one time of address change during RAS = V
IL
and CAS = V
IH.
I
CC4
is specified at one
time of address change during one Page cycle.
An Initial pause (RAS=CAS=V
IH
) of 200
μ
s is required after power-up followed by RAS only refresh cycle
or CAS before RAS refresh cycle (WE= ”H”) before proper device operation is achieved. In case of using
internal refresh counter, a minimum of eight CAS -before-RAS initialization cycles instead of RAS only
refresh cycle are required.
AC characteristics assume t
T
= 5 ns.
V
IH
(min.) and V
IL
(max.) are reference levels for measuring timing of input signals. Also transition times
are measured between V
IH
(min.) and V
IL
(max.).
Assumes that t
RCD
≤
t
RCD
(max.) and t
RAD
≤
t
RAD
(max.). If t
RCD
>
t
RCD
(max.) or t
RAD
>
t
RAD
(max.), t
RAC
will
be increased by the amount that t
RCD
or t
RCD
exceeds the maximum recommended value shown in this
table. Refer to Fig. 2 and 3.
If t
RCD
≥
t
RCD
(max.), t
RAD
≥
t
RAD
(max.), and t
ASC
≥
t
AA
– t
CAC
–
t
T
, access time is t
CAC
.
If t
RAD
≥
t
RAD
(max.) and t
ASC
≤
t
AA
– t
CAC
–
t
T
, access time is t
AA
.
Measured with a load equivalent to two TTL loads and 100 pF.
10. t
OFF
is specified that output buffer change to high impedance state.
11. Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
12. t
RCD
(min.) = t
RAH
(min.)+ 2 t
T
+ t
ASC
(min.).
13. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
14. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
15. t
WCS
, t
RWD,
t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If t
WCS
≥
t
WCS
(min.), the cycle is a Early-Write cycle and data out pin will
remain open circuit (high impedance) through the entire cycle. If t
WRD
≥
t
WRD
(min.), t
CWD
≥
t
CWD
(min.) and
t
AWD
≥
t
AWD
(min.), the cycle is a Read-Modify-Write cycle and data out pin will contain data read from the
selected cell. If WE is falled when neither of above sets of conditions is satisfied, the cycle is a Delayed-
Write cycle and the writing to the selected cell is executed when t
RWL
, t
CWL,
t
CAL
and t
RAL
are satisfied, but
the condition of the data out pin is indeterminated.
16. t
CPA
is access time from the selection of a new column address (that is caused by changing CAS from
“L” to “H”). Therefore, if t
CP
is long, t
CPA
is longer than t
CPA
(max.).
17. Assumes that CAS-before-RAS refresh.
18. Assumes that Test mode function.
19. If t
RCD
≤
t
RCD
(max.), t
DH
= 18 ns. Otherwise, t
DH
= 15 ns
2.
3.
4.
5.
6.
7.
8.
9.
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