參數(shù)資料
型號(hào)： MB814100D-60
廠商： Fujitsu Limited
英文描述： CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 1位快速頁(yè)面模式的DRAM（的CMOS 4米× 1位速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 20/23頁(yè)
文件大?。?/td> 238K
代理商： MB814100D-60
20
MB814100D-60/MB814100D-70
DESCRIPTION
Test Mode ;
The purpose of this test mode is to reduce device test time to one eighth of that required to test the device conventionally. The test
mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle.
In the test mode, read and write operations are executed in units of eight bits which are selected by the address
combination of RA
IO
, CA
O
and CA
IO
. In the write mode, data is written into eight cells simultaneously. In the read mode, the data of
eight cells at the selected addresses are read back and checked in the following manner.
When the eight bits are all ”L” or all ”H”, a ”H” level is output.
When the eight bits show a combination of ”L” and ”H”, a ”L” level is output.
The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle.
In test mode operation, the following parameters are delayed approximately 5 ns from the specified value in the data sheet.
t
RC
, t
RWC
, t
RAC
, t
AA
, t
RAS
, t
CSH
, t
RAL
, t
RWD
, t
AWD
, t
PC
, t
PRWC
, t
CPA
, t
RHCP
, t
CPWD
,
t
RASP
, t
RSH
, t
CAS
, t
CWD
, t
CAC
.
RAS
V
IH
V
IL
CAS
V
IH
V
IL
WE
V
IH
V
IL
D
OUT
V
OH
V
OL
Fig.14 – TEST MODE SET CYCLE (A
O
to A
IO
, D = ”H” or ”L”)
HIGH-Z
“H” or “L”
t
RC
t
RP
t
CPN
t
CSR
t
CHR
t
RPC
t
WSR
t
WHR
t
OFF
t
OH
t
RAS
t
RPC
相關(guān)PDF資料
PDF描述
MB814100D-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁(yè)面存取模式動(dòng)態(tài)RAM)
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MB814260-70 CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
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MB814265-70 CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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