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參數(shù)資料
| 型號： | MB8118165B-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 100萬× 16位的超頁模式動態(tài)RAM的CMOS（100萬× 16位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/28頁 |
| 文件大小： | 651K |
| 代理商： | MB8118165B-60 |
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DS05-10198-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
1 M
HYPER PAGE MODE DYNAMIC RAM
×
16 BITS
MB8118165B-50/-60
CMOS 1,048,576
×
16 BITS Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB8118165B is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 16-bit increments. The MB8118165B features a “hyper page” mode of operation whereby
high-speed random access of up to 1,024-bits of data within the same row can be selected. The MB8118165B
DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB8118165B is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB8118165B is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB8118165B are not critical and all inputs are TTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB8118165B-50
50 ns max.
84 ns min.
25 ns max.
15 ns max.
20 ns min.
990 mW max.
11 mW max. (LVTTL level)/5.5 mW max. (CMOS level)
MB8118165B-60
60 ns max.
104 ns min.
30 ns max.
15 ns max.
25 ns min.
825 mW max.
RAS Access Time
Random Cycle Time
Address Access Time
CAS Access Time
Hyper Page Mode Cycle Time
Low Power Dissipation
Operating current
Standby current
1,048,576 words
×
16 bits organization
Silicon gate, CMOS, Advanced stacked
Capacitor Cell
All input and output are TTL compatible
1,024 refresh cycles every 16.4 ms
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
Early write or OE controlled write capability
RAS-only, CAS-before-RAS, or Hidden Refresh
Hyper page mode, Read-Modify-Write capability
On chip substrate bias generator for high
performance
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