參數(shù)資料
型號(hào)： MB8117805B-50
廠商： Fujitsu Limited
英文描述： CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 200萬× 8位超頁模式動(dòng)態(tài)RAM的CMOS（200萬× 8位超級(jí)頁面存取模式動(dòng)態(tài)內(nèi)存）
文件頁數(shù)： 1/29頁
文件大?。?/td> 574K
代理商： MB8117805B-50
DS05-10199-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
2 M
HYPER PAGE MODE DYNAMIC RAM
×
8 BITS
MB8117805B-50/-60
CMOS 2,097,152
×
8 BITS Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB8117805B is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 8-bit increments. The MB8117805B features a “hyper page” mode of operation whereby high-
speed random access of up to 1024
×
8-bits of data within the same row can be selected. The MB8117805B
DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB8117805B is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB8117805B is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB8117805B are not critical and all inputs are TTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB8117805B-50
50 ns max.
84 ns min.
25 ns max.
15 ns max.
20 ns min.
715 mW max.
11 mW max. (TTL level)/5.5 mW max. (CMOS level)
MB8117805B-60
60 ns max.
104 ns min.
30 ns max.
15 ns max.
25 ns min.
605 mW max.
RAS Access Time
Random Cycle Time
Address Access Time
CAS Access Time
Hyper Page Mode Cycle Time
Low Power
Dissipation
Operating Current
Standby Current
2,097,152 words
×
8 bits organization
Silicon gate, CMOS, Advanced Capacitor Cell
All input and output are TTL compatible
2,048 refresh cycles every 32.8 ms
Early write or OE controlled write capability
RAS-only, CAS-before-RAS, or Hidden
Refresh
Hyper page mode, Read-Modify-Write
capability
On chip substrate bias generator for high
performance
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
相關(guān)PDF資料
PDF描述
MB8117805B-60 CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
MB8118160A-60 CMOS 1M×16 BIT Fast Page Mode Dynamic RAM(CMOS 1M×16 位快速頁面存取模式動(dòng)態(tài)RAM)
MB8118160A-70 CMOS 1M×16 BIT Fast Page Mode Dynamic RAM(CMOS 1M×16 位快速頁面存取模式動(dòng)態(tài)RAM)
MB8118165B-50 CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
MB8118165B-60 CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
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