參數(shù)資料
型號: MAX14830ETM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: SERIAL COMM CONTROLLER, QCC48
封裝: 7 X 7 MM, ROHS COMPLIANT, TQFN-48
文件頁數(shù): 57/68頁
文件大?。?/td> 2356K
代理商: MAX14830ETM+
MAX14830
Quad Serial UART with 128-Word FIFOs
and Internal Oscillator
60
issuing a STOP condition (P), to relinquish control of the
bus, or a Repeated START condition (Sr) to communi-
cate to another I2C slave. See Figure 21.
Slave Address
The MAX14830 includes a 7-bit I2C slave address, allow-
ing up to 16 MAX14830 devices to share the same I2C
bus. The first 5 bits (MSBs) of the slave address are
factory programmed and are predefined for each of the
four UARTs (UART0, UART1, UART2, and UART3). The
two LSBs of the address are defined by connecting the
MOSI/A1 and CS/A0 inputs to ground, VL, SDA or to
SCL (Table 12). Set the read/write bit to 1 to configure
the MAX14830 to read mode. Set the read/write bit to 0
to configure the MAX14830 to write mode. The address
is the first byte of information sent to the MAX14830 after
the START condition.
Figure 21. I2C START, STOP and REPEATED START Conditions
Table 12. I2C Address Map
SCL
SDA
S
Sr
P
MOSI/A1
CS/A0
UART0
UART1
UART2
UART3
WRITE
READ
WRITE
READ
WRITE
READ
WRITE
READ
DGND
0xD8
0xD9
0xB8
0xB9
0x58
0x59
0x38
0x39
DGND
VL
0xC2
0xC3
0xA2
0xA3
0x42
0x43
0x22
0x23
DGND
SCL
0xC4
0xC5
0xA4
0xA5
0x44
0x45
0x24
0x25
DGND
SDA
0xC6
0xC7
0xA6
0xA7
0x46
0x47
0x26
0x27
VL
DGND
0xC8
0xC9
0xA8
0xA9
0x48
0x49
0x28
0x29
VL
0xCA
0xCB
0xAA
0xAB
0x4A
0x4B
0x2A
0x2B
VL
SCL
0xCC
0xCD
0xAC
0xAD
0x4C
0x4D
0x2C
0x2D
VL
SDA
0xCE
0xCF
0xAE
0xAF
0x4E
0x4F
0x2E
0x2F
SCL
DGND
0xD0
0xD1
0xB0
0xB1
0x50
0x51
0x30
0x39
SCL
VL
0xD2
0xD3
0xB2
0xB3
0x52
0x53
0x32
0x39
SCL
0xD4
0xD5
0xB4
0xB5
0x54
0x55
0x34
0x39
SCL
SDA
0xD6
0xD7
0xB6
0xB7
0x56
0x57
0x36
0x39
SDA
DGND
0xC0
0xC1
0xA0
0xA1
0x40
0x41
0x20
0x21
SDA
VL
0xDA
0xDB
0xBA
0xBB
0x5A
0x5B
0x3A
0x3B
SDA
SCL
0xDC
0xDD
0xBC
0xBD
0x5C
0x5D
0x3C
0x3D
SDA
0xDE
0xDF
0xBE
0xBF
0x5E
0x5F
0x3E
0x3F
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