參數(shù)資料
型號(hào): MAX14830ETM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: SERIAL COMM CONTROLLER, QCC48
封裝: 7 X 7 MM, ROHS COMPLIANT, TQFN-48
文件頁(yè)數(shù): 38/68頁(yè)
文件大?。?/td> 2356K
代理商: MAX14830ETM+
MAX14830
Quad Serial UART with 128-Word FIFOs
and Internal Oscillator
43
IrDA Register
The IrDA register allows selection of IrDA SIR- and MIR-compliant pulse shaping at the TX_ and RX_ interfaces. It also
allows inversion of the TX_ and RX_ logic, independently of whether IrDA is enabled or not.
Bits 7, 6: No Function
Bit 5: TxInv
Set the TxInv bit high to invert the logic at the TX_ output. This is independent of IrDA operation.
Bit 4: RxInv
Set the RxInv bit high to invert the logic state at the RX_ input. This is independent of IrDA operation.
Bit 3: MIR
Set the MIR and IrDAEn bits high to select IrDA 1.1 (MIR) with 1/4 period pulse widths.
Bit 2: ShortIR
Set the ShortIR and IrDAEn bits high to select IrDA 1.0 (SIR) with the transmitter producing the minimum allowed pulse
widths of 1.63Fs.
Bit 1: SIR
Set the SIR bit and the IrDAEn bits high to select IrDA 1.0 pulses (SIR) with 3/16th period pulses.
Bit 0: IrDAEn
Set the IrDAEn bit high so that IrDA compliant pulses are produced at the TX_ output and the MAX14830 receiver
expects such pulses at its Rx input. If IrDA[0] is set to low (default), normal (non-IrDA) pulses are generated and
expected at the receiver. IrDAEn must be used in conjunction with the SIR, ShortIR, or MIR select bits.
ADDRESS:
0x0E
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
TxInv
RxInv
MIR
ShortIR
SIR
IrDAEn
RESET
0
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參數(shù)描述
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