
MAX14830
Quad Serial UART with 128-Word FIFOs
and Internal Oscillator
20
The receiver can be turned off through MODE1[0]:
RxDisabl. When this bit is set to 1, the MAX14830 turns
the receiver off immediately following the current word
and does not receive any further data.
The RX_ input logic can be inverted through IrDA[4]:
RxInv.
Line Noise Indication
When operating in standard or 2x (i.e. not 4x) rate mode,
the MAX14830 checks that the binary logic level of the
three samples per received bit are identical. If any of
the three samples have differing logic levels, then noise
on the transmission line has affected the received data
and is considered to be noisy. This noise indication is
reflected in the LSR[5]: RxNoise bit for each received
byte. Parity errors are another indication of noise, but are
not as sensitive.
Clocking and Baud-Rate Generation
The MAX14830 can be clocked by its internal oscillator,
an external crystal, or an external clock source. Figure 7
shows a simplified diagram of the clocking circuitry.
When the MAX14830 is clocked by the internal oscillator
or a crystal, the STSInt[5]: ClockReady indicates when
the clocks have settled and the baud-rate generator is
ready for stable operation.
Each UART baud rate can be individually programmed.
The baud-rate clock can be routed to the RTS_ output.
The clock rate of this is 16x the baud rate in standard
operating mode and 8x the baud rate in 2x rate mode.
In 4x rate mode, the CLKOUT frequency is 4x the
programmed baud rate. If the fractional portion of the
baud-rate generator is used, the clock is not regular and
exhibits jitter.
Internal Oscillator
The internal 614.4kHz oscillator does not require exter-
nal components and provides a source for baud-rate
generation. To achieve common baud rates, the inter-
nal oscillator requires the use of the internal PLL (see
the PLL section). Set CLKSource[4]: ExtClock to 0 and
CLKSource[0]: IntOscEn to 1 to select and enable the
internal oscillator.
Crystal Oscillator
If a higher baud-rate accuracy or low power consump-
tion is required, the crystal oscillator or an external clock
source can be used. Set CLKSource[4]: ExtClock to 1
and CLKSource[1]: CrystalEn to 1 to enable and select
the crystal oscillator. The on-chip crystal oscillator has
load capacitances of 16pF (typ) integrated in both XIN
and XOUT. Connect an external crystal or ceramic oscil-
lator between XIN and XOUT.
External Clock Source
Connect an external clock source to XIN when not using
the internal oscillator or a crystal oscillator. Leave XOUT
unconnected. Set CLKSource[4]: ExtClock to 1 and
CLKSource[1]: CrystalEn to 0 to select external clocking.
PLL and Predivider
The internal predivider and PLL allow for a wide range of
external clock frequencies and baud rates. The PLL can
be configured to multiply the input clock rate by a factor
of 6, 48, 96, or 144 through the PLLConfig register. The
predivider, located between the input clock and the PLL,
allows division of the input clock by a factor between 1
and 63 by writing to PLLConfig[5:0]. See the PLLConfig
register description for more information.
Figure 7. Clock Selection Diagram
PLLByps
ExtClock
CrystalEn
XOUT
CRYSTAL
OSCILLATOR
INTERNAL
OSCILLATOR
IntOscEn
PLLEn
XIN
DIVIDER
PLL
FRACTIONAL
BAUD-RATE
GENERATOR 1
FRACTIONAL
BAUD-RATE
GENERATOR 2
FRACTIONAL
BAUD-RATE
GENERATOR 3
FRACTIONAL
BAUD-RATE
GENERATOR 0