參數(shù)資料
型號: MAX14830ETM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: SERIAL COMM CONTROLLER, QCC48
封裝: 7 X 7 MM, ROHS COMPLIANT, TQFN-48
文件頁數(shù): 55/68頁
文件大?。?/td> 2356K
代理商: MAX14830ETM+
MAX14830
Quad Serial UART with 128-Word FIFOs
and Internal Oscillator
59
Fast Read Cycle
On the MAX14830 the four UART interrupts share the
single IRQ output. When operating in interrupt-based
mode, the microcontroller needs to locate the source of
the interrupt (i.e. which of the four UARTs generated the
interrupt) and clear the interrupt.
To locate the source of an interrupt more quickly, the
MAX14830 implements the SPI fast read cycle. This
means that the microcontroller can determine which
UART is the source of the interrupt (UART0, UART1,
UART2, or UART3) using only 8 clock cycles (Figure 20).
U1 and U0 bits are ignored during the fast read cycle.
I2C Interface
The MAX14830 contains an I2C-compatible interface
for data communication with a host processor (SCL and
SDA). The interface supports a clock frequency up to
1MHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
START, STOP, and Repeated START Conditions
When writing to the MAX14830 using I2C, the master
sends a START condition (S) followed by the MAX14830
I2C address. After the address, the master sends
the register address of the register that is to be pro-
grammed. The master then ends communication by
Figure 19. SPI Read Cycle
Figure 20. SPI Fast Read Cycle
HIGH-Z
Ax = REGISTER ADDRESS
Dx = EIGHT-BIT REGISTER CONTENTS
SCLK
MOSI
MISO
R
U1
U0
A4
A3
A2
A1
A0
CS
IRQ3
IRQ2
IRQ1
IRQ0
D7
D6
D5
D4
D3
D2
D1
D0
MOSI
Ax = REGISTER ADDRESS
SCLK
CS
MISO
U1
HIGH-Z
R
U0
A4
A3
A2
A1
A0
IRQ3
IRQ2
IRQ1
IRQ0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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