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參數(shù)資料
| 型號： | M66273FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | LCD CONTROLLER with VRAM |
| 中文描述： | 液晶顯示控制器顯存 |
| 文件頁數(shù)： | 31/34頁 |
| 文件大小： | 297K |
| 代理商： | M66273FP |
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LCD CONTROLLER with VRAM
M66273FP
MITSUBISHI <DIGITAL ASSP>
Ver.3.1 Dec,1999
(7) Write to VRAM ( RD = "H" )
Term of cycle steal access (and When setting register WAITC to "1")
tC(CLK)
tsu(MCS-WC)
tsu(A-WR)
th(WR-A)
tw(MCS)
th(MCS-A)
th(MCS-D)
Address is established
Data input is established
tC(CLK)
tWL(CLK)
ta(RD-D)
tsu(MCS-WC)
tsu(A-RD)
th(RD-A)
th(MCS-A)
tdis(MCS-D)
tpHL(WC-WAIT)
tpLH(CLK-WAIT)
tpd(D-WAIT)
Data output is established
Address is established
tWH(CLK) tWL(CLK)
th(WR-D)
Term of cycle steal access (and when setting register WAITC to "1")
(8) Read from VRAM ( LWR, HWR = "H")
tWH(CLK)
tdis(RD-D)
Note 7 : Writing/reading operation for VRAM during cycle steal access needs 0.5tc(MAINCLK) + 1tc(CLK) in best case or 2.5tc(MAINCLK)+1tc(CLK) in
worst case, according to the condition of the internal cycle steal at starting access requested from MPU.
Data output D is established before changing WAIT output.
tc(
MAINCLK
) = Reference clock cycle time for internal operation after setting division of MPUCLK.
8 : When setting WAITC to "1" , MCS is necessary to change "L" earier than LWR (+HWR) ,RD.
Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first
change to "H" in ending access.
9 : Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as next WAIT does not output, this
causes malfunction to occur.
31
tsu(D-CLK)
MPUCLK
MCS
WAIT
D<7:0>
(D<15:0>)
WAITCNT
A<14:0>
(+BHE)
LWR
(+HWR)
tpLH(CLK-WAIT)
tpHL(WC-WAIT)
MPUCLK
MCS
WAIT
D<7:0>
(D<15:0>)
RD
A<14:0>
WAITCNT
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