參數(shù)資料
型號: M66273FP
廠商: Mitsubishi Electric Corporation
英文描述: LCD CONTROLLER with VRAM
中文描述: 液晶顯示控制器顯存
文件頁數(shù): 27/34頁
文件大?。?/td> 297K
代理商: M66273FP
LCD CONTROLLER with VRAM
M66273FP
MITSUBISHI <DIGITAL ASSP>
Ver.3.1 Dec,1999
P.G
DUT
Input
V
DD
Outputs
except for
D<15:0>
50
Ohm
C
L
V
DD
R
L
=1K
Ohm
R
L
=1K
Ohm
SW1
SW2
D<15:0>
C
L
V
SS
Parameter
t
dis
(LZ)
t
dis
(HZ)
t
a
(ZL)
t
a
(ZH)
SW1
Closed
Open
SW2
Open
Closed
Open
Input pulse level: 0 to 3V
Input pulse rise/fall time: tr,tf=3ns
Input decision voltage: 1.5V
Output decision voltage: VDD/2
(However,tdis(LZ) is 10% of output amplitude and
tdis(HZ) is 90% of that for dezision.)
Load capacity C
L
include float capacity of
connection and input capacity of probe.
(1)
(2)
Test circuit
Closed
Open
Closed
t
WH(CLK)
50
ns
t
WL(CLK)
ns
t
WH(CP)
ns
t
WL(CP)
t
WH(CP)
ns
t
WL(CP)
t
W(FLM)
ns
t
C(CP)
ns
ns
t
c(CLK)
ns
Symbol
Parameter
Test
condition
Limits
Typ.
Min.
Max.
Unit
MPUCLK "H" pulse width
MPUCLK cycle time
MPUCLK "L" pulse width
CP syscle time
CP "H" pulse width
CP "L" pulse width
CP "H" pulse width
CP "L" pulse width
FLM pluse width
(3) Clock and accessing to LCD display
Display mode 1,2,3,5,6
Display mode 4
Display mode 1,2,3,5,6
Display mode 4
Display mode 1,2,3,5,6
Display mode 4
t
C(CLK)
2
t
C(CLK)
(1/n)
2 · t
C(CLK)
(1/n)
t
C(CLK)
2 · (1/n)
t
C(CLK)
(1/n)
t
C(CLK)
·
LPW
(1/n)
2 · t
C(CLK)
·
LPW
(1/n)
Note : Clock frequency of MPUCLK input is less than fmax = 20MHz.
Limit of clock for the internal operation is fmax = 10MHz.
When MPUCLK is more than 10MHz from extemal input,set clock for the internal operation
up to 10MHz by using division of DIV register.
Division is set with rising dege of MPUCLK input.
1/n =Division of MPUCLK
LPW =Setting value of LPW register
27
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