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參數(shù)資料
| 型號： | M66281FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 5120 x 8-BIT x 2 LINE MEMORY |
| 中文描述： | 5120 × 8位× 2列內(nèi)存 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 125K |
| 代理商： | M66281FP |
5120 x 8-BIT x 2 LINE MEMORY
M66281FP
MITSUBISHI <DIGITAL ASSP>
DESCRIPTION
The M66281FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts the
FIFO (First In First Out) structure consisting of 5120 words x 8 bits
x 2.
Since memory is available to simultaneously output 1 line delay and
2 line delay data, the M66281FP is optimal for the compensation of
data of multiple lines.
FEATURES
Memory configuration 5120 words x 8 bits x 2 (dynamic memory)
High speed cycle
25 ns (Min.)
High speed access
18 ns (Max.)
Output hold
3 ns (Min.)
Reading and writing operations can be completely carried out
independently and asynchronously.
Variable length delay bit
Input/output
TTL direct connection allowable
Output
3 states
Q00 – Q07
1 line delay
Q10 – Q17
2 line delay
APPLICATION
Digital copying machine
,
laser beam printer, high speed facsimile,
etc.
FUNCTION
When write enable input WEB is set to "L", the contents of data
inputs D0 to D7 are written into memory only for 1 line delay data in
synchronization with a rising edge of write clock input WCK to
perform writing operation. When this is the case, the write address
counter of memory only for 1 line delay data is incremented
simultaneously.
When WEB is set to "H", the writing operation is inhibited and the
write address counter of memory only for 1 line delay data stops.
When write reset input WRESB is set to "L", the write address
counter of memory only for 1 line delay data is initialized.
When read enable input REB is set to "L", the contents of memory
only for 1 line delay data are output to data outputs Q00 to Q07
and the contents of memory only for 2 line delay data are output to
Q10 to Q17 in synchronization with a rising edge of read clock
input RCK to perform reading operation.
When this is the case, the read address counters of memory only
for 1 line delay data and memory only for 2 line delay data are
incremented simultaneously.
In addition, data of Q00 to Q07 is written into memory only for 2
line delay data in synchronization with a rising edge of RCK. When
this is the case, the write address counter of memory only for 2 line
delay data is then incremented.
When REB is set to "H", operation for reading data from memory
only for 1 line delay and from memory only for 2 line delay data is
inhibited and the read address counter of each memory stops.
Outputs Q00 to Q07 and Q10 to Q17 are placed in a high
impedance state. In addition, the write address counter of memory
only for 2 line delay data then stops.
When read reset input RRESB is set to "L", the read address
counters of memory only for 1 line delay data as well as the write
address counter and read address counter of memory only for 2
line delay data are then initialized.
PIN CONFIGURATION (TOP VIEW)
Outline 48P6S-A(QFP)
3
3
3
3
3
3
3
2
2
2
2
2
1
2
3
4
5
6
7
8
9
1
1
1
3
3
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
1
1
N
N
Q
Q
Q
Q
Q
G
V
C
Q
Q
Q
Q
Q
NC
Q15
Q16
Q17
V
CC
GND
D7
D6
D5
NC
N
N
D
D
D
D
D
V
C
G
W
W
W
N
N
NC
RCK
RRESB
REB
GND
V
CC
Q00
Q01
Q02
NC
M66281FP
NC : No connection
1
相關PDF資料 |
PDF描述 |
|---|---|
| M66282FP | 8192 x 8-BIT LINE MEMORY |
| M66290AFP | USB DEVICE CONTROLLER |
| M66290AGP | USB DEVICE CONTROLLER |
| M66300FP | PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO |
| M66300P | PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M66282FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 8-BIT LINE MEMORY |
| M66282FP(#TB0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66287FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-word x 8-bit x 3-FIELD MEMORY |
| M66288FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:262144-word x 8-bit x 3-FIFO MEMORY |
| M66290AFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:USB DEVICE CONTROLLER |
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