- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384643 > M66273FP (Mitsubishi Electric Corporation) LCD CONTROLLER with VRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | M66273FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | LCD CONTROLLER with VRAM |
| 中文描述： | 液晶顯示控制器顯存 |
| 文件頁數(shù)： | 30/34頁 |
| 文件大?。?/td> | 297K |
| 代理商： | M66273FP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁
LCD CONTROLLER with VRAM
M66273FP
MITSUBISHI <DIGITAL ASSP>
Ver.3.1 Dec,1999
(5) Write to VRAM ( RD = "H",WAITCNT= "L" or "H" fixed )
Term of cycle steal access (and When setting register WAITC to "0")
tC(CLK)
tsu(A-MCS)
tsu(A-WR)
th(WR-A)
tw(WR)
tw(MCS)
th(MCS-A)
th(MCS-D)
tpHL(MCS-WAIT)
tpHL(WR-WAIT)
tpLH(CLK-WAIT)
Address is established
Data input is established
tC(CLK)
tWL(CLK)
ta(RD-D)
ta(MCS-D)
tsu(A-MCS)
tsu(A-RD)
th(RD-A)
th(MCS-A)
tdis(MCS-D)
tpHL(MCS-WAIT)
tpHL(RD-WAIT)
tpLH(CLK-WAIT)
tpd(D-WAIT)
Data output is established
Address is established
MPUCLK
MCS
WAIT
D<7:0>
(D<15:0>)
LWR
(+HWR)
A<14:0>
(+BHE)
MPUCLK
MCS
WAIT
D<7:0>
(D<15:0>)
RD
A<14:0>
tWH(CLK) tWL(CLK)
th(WR-D)
Term of cycle steal access (and when setting segester WAITC to "0")
(6) Read from VRAM( LWR, HWR = "H",WAITCNT = "L" or "H" fiexed)
tWH(CLK)
tdis(RD-D)
Note 4 :Writing/reading operation for VRAM during cycle steal access needs 0.5tc(MAINCLK) + 1tc(CLK) in best case or 2.5tc(MAINCLK)+1tc(CLK) in
worst case, according to the condition of the internal cycle steal at starting access requested from MPU.
Data output D is established before changing WAIT output.
tc(
MAINCLK
) = Reference clock cycle time for internal operation after setting division of MPUCLK.
5 : Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to
"L" in starting access, and by the input signal of
first change to "H" in ending access.
6 : Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as next WAIT does not output, this
causes malfunction to occur.
30
tsu(D-CLK)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66280FP | 5120 x 8-BIT LINE MEMORY |
| M66281FP | 5120 x 8-BIT x 2 LINE MEMORY |
| M66282FP | 8192 x 8-BIT LINE MEMORY |
| M66290AFP | USB DEVICE CONTROLLER |
| M66290AGP | USB DEVICE CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66280FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT LINE MEMORY |
| M66280FP(#TB0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66281FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120 × 8-Bit × 2 Line Memory |
| M66282FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 8-BIT LINE MEMORY |
| M66282FP(#TB0T) | 制造商:Renesas Electronics Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。