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參數(shù)資料
| 型號： | M66273FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | LCD CONTROLLER with VRAM |
| 中文描述： | 液晶顯示控制器顯存 |
| 文件頁數(shù)： | 26/34頁 |
| 文件大?。?/td> | 297K |
| 代理商： | M66273FP |
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LCD CONTROLLER with VRAM
M66273FP
MITSUBISHI <DIGITAL ASSP>
Ver.3.1 Dec,1999
SWITCHING CHARACTERISTICS (V
DD
=3V
±
10%, Ta=-20~+75 )
TIMING REQUIREMENTS (V
DD
=3V
±
10%, Ta=-20~+75 )
(1) Accessing to control register
3V version support spcification
ta(RD-D)
tdis(IOCS-D)
tdis(MCS-D)
100
ns
tdis(RD-D)
tpHL(MCS-WAIT)
30
ns
tpd(CLK-CP)
40
ns
tpLH(CLK-LP)
tpHL(CLK-LP)
40
ns
ta(VD)
40
ns
tpLH(CLK-FLM)
tpHL(CLK-FLM)
40
ns
tpd(CLK-M)
40
ns
tpLH(CLK-LE)
tpHL(CLK-LE)
tpLH(CLK-CSE)
tpHL(CLK-CSE)
40
ns
tpHL(WR-WAIT)
tpHL(RD-WAIT)
tpHL(WC-WAIT)
tpLH(CLK-WAIT)
25
ns
25
ns
CL=50pF
ta(IOCS-D)
ta(MCS-D)
tpd(D-WAIT)
0
ns
Symbol
Parameter
Test
condition
Limits
Typ.
Min.
Max.
Unit
RD data access time
Output disable time after IOCS
Output disable time after MCS
IOCS data access time
MCS data access time
Output disable time after RD
WAIT output propagation time after MCS
t
W(LWR)
t
su(D-CS)
50
ns
t
su(D-LWR)
t
h(CS-D)
ns
t
h(LWR-D)
t
su(A-CS)
t
su(A-LWR)
t
su(A-RD)
t
h(CS-A)
2
ns
15
ns
t
h(LWR-A)
t
h(RD-A)
0
ns
t
W(CS)
Symbol
Parameter
Test
condition
Limits
Typ.
Unit
Min.
Max.
LWR pulse width
Data set up time before rising edge of IOCS/MCS
IOCS/MCS pulse width
Data set up time before rising edge of LWR
Data hold time after rising edge of IOCS/MCS
Data hold time after rising edge of LWR
Address set up time before falling edge of IOCS/MCS
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
Address hold time after rising edge of IOCS/MCS
(2) Accessing to VRAM
t
W(WR)
t
su(D-MCS)
ns
t
su(D-WR)
t
h(MCS-D)
ns
t
h(WR-D)
t
su(A-MCS)
t
su(A-WR)
t
su(A-RD)
t
h(MCS-A)
ns
ns
t
h(WR-A)
t
h(RD-A)
t
su(D-CLK)
ns
t
W(MCS)
Symbol
Parameter
Test
condition
Limits
Typ.
Unit
Min.
Max.
WR pulse width
Data set up time before rising edge of MCS
MCS pulse width
Data set up time before rising edge of WR
Data hold time after rising edge of MCS
Data hold time after rising edge of WR
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
Address hold time after rising edge of MCS
Address hold time after rising edge of WR
Address hold time after rising edge of RD
40
ns
WAIT output propagation time after MPUCLK
CP output propagation time after MPUCLK
LP output propagation time after MPUCLK
VD access time
FLM output propagation time after MPUCLK
M output propagation time after MPUCLK
LCDENB output propagation time after MPUCLK
Data definite time before cancelling WAIT
CSE output propagation time after MPUCLK
50
2
15
0
26
WAIT output propagation time after WR
WAIT output propagation time after RD
WAIT output propagation time after WAITCNT
30
30
t
su(MCS-WC)
ns
MCS set up time before falling edge of WAITCNT
Data set up time before rising edge of WAIT
7
t
c(CLK)+15
ns
* tc(CLK)=MPUCLK cycle time
C
C
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