參數(shù)資料
型號(hào)： M38C2XMX
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 48/63頁(yè)
文件大小： 1000K
代理商： M38C2XMX
48
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
CLOCK GENERATING CIRCUIT
The 38C2 group has two built-in oscillation circuits; main clock X
IN
–
X
OUT
and sub-clock X
CIN
–X
COUT
. An oscillation circuit can be formed
by connecting a resonator between X
IN
and X
OUT
(X
CIN
and X
COUT
).
Use the circuit constants in accordance with the resonator
manufacturer’s recommended values. No external resistor is needed
between X
IN
and X
OUT
since a feedback resistor exists on-chip. How-
ever, an external feedback resistor is needed between X
CIN
and
X
COUT
.
When the clock signal is supplied from external for the main clock,
input the signal to X
IN
pin and input the inverted-phase signal of X
IN
to X
OUT
pin by the external inverter.
When the clock signal is supplied from external for the sub-clock,
input the signal to X
CIN
and leave X
COUT
open.
Immediately after power on, only the X
IN
oscillation circuit starts os-
cillating.
Frequency Control
(1) Frequency/8 Mode
The system clock
φ
is the frequency of X
IN
divided by 8. After reset is
released, this mode is selected.
(2) Frequency/4 Mode
The system clock
φ
is the frequency of X
IN
divided by 4.
(3) Frequency/2 Mode
The system clock
φ
is the frequency of X
IN
divided by 2.
(4) Through Mode
The system clock
φ
is the frequency of X
IN
.
(5) Low-speed Mode
The system clock
φ
is the frequency of X
CIN
divided by 2. In the low-
speed mode, the low-power dissipation operation can be performed
when the main clock X
IN
is stopped by setting the bit 7 of the CPU
mode register to “0”. In this case, when main clock X
IN
oscillation is
restarted, generate the wait time until the oscillation is stable by pro-
gram after the bit 7 of the CPU mode register is set to “1”.
Fig. 50 Ceramic resonator circuit
Fig. 51 External clock input circuit
X
O
U
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Notes on Clock Generating Circuit
If you switch the mode between through, frequency/2/4, or 8 and
low-speed, stabilize both X
IN
and X
CIN
oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately after
power on and at returning from stop mode. When switching the mode,
set the frequency on condition that f(X
IN
) > 3f(X
CIN
).
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the system clock
φ
stops at an
“
H
”
level, and main clock and sub-clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Set the values to
generate the wait time required for oscillation stabilization to timer 1
latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8
bits of timer 2) before the STP instruction.
The frequency divider for timer 1 is used for the timer 1 count source,
and the output of timer 1 is forcibly connected to timer 2. In this time,
bits 0 to 5 of the timer 12 mode register are cleared to
“
0
”
.
The values of the timer 12 frequency divider selection register are
not changed.
Set the interrupt enable bits of the timer 1 and timer 2 to disabled
(
“
0
”
) before executing the STP instruction.
Oscillator restarts When reset occurs or an interrupt request is re-
ceived, but the system clock
φ
is not supplied to the CPU until timer
2 underflows. This allows time for the clock circuit oscillation to stabi-
lize.
(2) Wait Mode
If the WIT instruction is executed, the system clock
φ
stops at an
“
H
”
level. The states of X
IN
and X
CIN
are the same as the state before
executing the WIT instruction. The system clock
φ
restarts at reset or
when an interrupt is received. Since the oscillator does not stop, nor-
mal operation can be started immediately after the clock is restarted.
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