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參數(shù)資料
| 型號： | M38C2XMX |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 33/63頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | M38C2XMX |
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33
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 29 Structure of serial I/O related registers
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns
“
1
”
when read)
Serial I/O status register
(SIO1STS : address 001D
16
)
[SIO2STS : address 001F
16
]
Serial I/O control register
(SIO1CON : address 0FE0
16
)
[SIO2CON : address 0FE3
16
]
b0
b0
BRG count source selection bit (CSS)
0: f(X
IN
) (f(X
CIN
) in low-speed mode)
1: f(X
IN
)/4 (f(X
CIN
)/4 in low-speed mode)
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected.
External clock input divided by 16 when UART is selected.
S
RDY
output enable bit (SRDY)
0: P5
7
[P3
0
] pin operates as ordinary I/O pin
1: P5
7
[P3
0
] pin operates as S
RDY
output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P5
4
[P3
0
] to P5
7
[P3
3
] operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P5
4
[P3
0
] to P5
7
[P3
3
] operate as serial I/O pins)
b7
UART control register
(UART1CON : address 0FE1
16
)
[UART2CON : address 0FE4
16
]
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P5
5
/TXD
1
[P3
2
/TxD
2
] P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return
“
1
”
when read)
b0
( ) : For Serial I/O1
[ ] : For Serial I/O2
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