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參數資料
| 型號： | M38C2XMX |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數： | 37/63頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | M38C2XMX |
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37
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Duty
ratio
2
3
4
Voltage value
V
L3
=V
LCD
V
L2
=2/3 V
LCD
V
L1
=1/3 V
LCD
V
L3
=V
LCD
V
L2
=V
L1
=1/2 V
LCD
Bias Control and Applied Voltage to LCD Power
Input Pins
When the voltage is applied from the LCD power input pins (V
L1
–
V
L3
), set the VL pin input selection bit (bit 5 of the LCD power control
register) and V
L3
connection bit (bit 6 of LCD power control register)
to
“
1
”
, apply the voltage value shown in Table 9 according to the bias
value. In this case, SEG
22
pin and SEG
23
pin cannot be used.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Fig. 34 Example of circuit at each bias (at external power input)
Table 9 Bias control and applied voltage to V
L1
–V
L3
Bias value
1/3 bias
1/2 bias
Note :
V
LCD
is the maximum value of supplied voltage for the LCD panel.
Table 10 Duty ratio control and common pins used
Note:
Unused common pin outputs the unselected waveform.
Common pins used
COM
0
, COM
1
COM
0
–
COM
2
COM
0
–
COM
3
Bit 1
0
1
1
Bit 0
1
0
1
Duty ratio selection bit
Common Pin and Duty Ratio Control
The common pins (COM
0
–
COM
3
) to be used are determined by duty
ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of
the LCD mode register). When reset is released, V
CC
voltage is out-
put from the common pin.
Segment Signal Output Pin
The segment signal output pins (SEG
0
–
SEG
23
) are shared with ports
P0
–
P2. When these pins are used as the segment signal output pins,
set the direction registers of the corresponding pins to
“
1
”
, and clear
the segment output disable register to
“
0
”
.
Also, these pins are set to the input port after reset, the V
CC
voltage
is output by the pull-up resistor.
V
L3
V
L2
V
L1
R
4
R5
R4 = R5
C
o
n
t
r
a
s
t
a
d
j
u
s
t
1/2 bias
V
L
3
V
L
2
V
L
1
C
o
n
t
r
a
s
t
a
d
j
u
s
t
R1
R
2
R3
R
1
=
R
2
=
R
3
1
/
3
b
i
a
s
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