參數資料
型號： M38C2XMX
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數： 35/63頁
文件大?。?/td> 1000K
代理商： M38C2XMX
35
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
LCD DRIVE CONTROL CIRCUIT
The 38C2 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output disable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 24 segment output pins and 4 common output pins
can be used.
Up to 96 pixels can be controlled for an LCD display. When the LCD
enable bit is set to
“
1
”
after data is set in the LCD mode register, the
Fig. 32 Structure of LCD related registers
segment output disable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
Table 8 Maximum number of display pixels at each duty ratio
Duty ratio
2
3
4
Maximum number of display pixels
48 dots
or 8 segment LCD 6 digits
72 dots
or 8 segment LCD 9 digits
96 dots
or 8 segment LCD 12 digits
Segment output disable bit 0
0 : Segment output SEG
0
1 : Output port P0
0
Segment output disable bit 1
0 : Segment output SEG
1
1 : Output port P0
1
Segment output disable bit 2
0 : Segment output SEG
2
1 : Output port P0
2
Segment output disable bit 3
0 : Segment output SEG
3
1 : Output port P0
3
Segment output disable bit 4
0 : Segment output SEG
4
1 : Output port P0
4
Segment output disable bit 5
0 : Segment output SEG
5
1 : Output port P0
5
Segment output disable bit 6
0 : Segment output SEG
6
1 : Output port P0
6
Segment output disable bit 7
0 : Segment output SEG
7
1 : Output port P0
7
Segment output disable register 0
(SEG0 : address 0FF8
16
)
b7
b0
LCD mode register
(LM : address 0039
16
)
Duty ratio selection bits
b1 b0
0 0 : Not used
0 1 : 2 (use COM
0
,COM
1
)
1 0 : 3 (use COM
0
–
COM
2
)
1 1 : 4 (use COM
0
–
COM
3
)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD drive timing selection bit
0 : Type A
1 : Type B
LCD circuit divider division ratio selection bits
b6 b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit
(Note)
0 : f(X
CIN
)/32
1 : f(X
IN
)/8192 (f(X
CIN
)/8192 in low-speed mode)
Note :
LCDCK is a clock for an LCD timing controller.
b7
b0
Segment output disable bit 8
0 : Segment output SEG
8
1 : Output port P1
0
Segment output disable bit 9
0 : Segment output SEG
9
1 : Output port P1
1
Segment output disable bit 10
0 : Segment output SEG
10
1 : Output port P1
2
Segment output disable bit 11
0 : Segment output SEG
11
1 : Output port P1
3
Segment output disable bit 12
0 : Segment output SEG
12
1 : Output port P1
4
Segment output disable bit 13
0 : Segment output SEG
13
1 : Output port P1
5
Segment output disable bit 14
0 : Segment output SEG
14
1 : Output port P1
6
Segment output disable bit 15
0 : Segment output SEG
15
1 : Output port P1
7
Segment output disable register 1
(SEG1 : address 0FF9
16
)
b7
b0
Segment output disable bit 16
0 : Output port P2
0
1 : Segment output SEG
16
Segment output disable bit 17
0 : Output port P2
1
1 : Segment output SEG
17
Segment output disable bit 18
0 : Output port P2
2
1 : Segment output SEG
18
Segment output disable bit 19
0 : Output port P2
3
1 : Segment output SEG
19
Segment output disable bit 20
0 : Output port P2
4
1 : Segment output SEG
20
Segment output disable bit 21
0 : Output port P2
5
1 : Segment output SEG
21
Segment output disable bit 22
0 : Output port P2
6
1 : Segment output SEG
22
Segment output disable bit 23
0 : Output port P2
7
1 : Segment output SEG
23
Segment output disable register 2
(SEG2 : address 0FFA
16
)
b7
b0
Note :
Only pins set to output ports by the direction register can be controlled to switch
to output ports or segment outputs by the segment output disable register.
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