參數(shù)資料
型號： M38869MFAHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 64/111頁
文件大小： 1644K
代理商： M38869MFAHP
56
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
for flash
memory
version
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Fig. 56 Internal status at reset
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
I2C data shift register (S0)
I2C address register (S0D)
I2C status register (S1)
I2C control register (S1D)
I2C clock control register (S2)
I2C start/stop condition control register (S2D)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Serial I/O2 control register (SIO2CON)
Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Data bus buffer register 0 (DBB0)
Data bus buffer status register 0 (DBBSTS0)
Data bus buffer control register (DBBCON)
Data bus buffer register 1 (DBB1)
Data bus buffer status register 1 (DBBSTS1)
Comparator data register (CMPD)
Port control register 1 (PCTL1)
Port control register 2 (PCTL2)
PWM0H register (PWM0H)
PWM0L register (PWM0L)
PWM1H register (PWM1H)
PWM1L register (PWM1L)
AD/DA control register (ADCON)
A-D conversion register 1 (AD1)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
A-D conversion register 2 (AD2)
Interrupt source selection register (INTSEL)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Flash memory control register (FCON)
Flash command register (FCMD)
Processor status register
Program counter
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
(67)
(68)
Register contents
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
0FFE16
0FFF16
(PS)
(PCH)
(PCL)
Address
Note :
X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
FF16
0116
FF16
0016
FF16
0016
Address Register contents
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
0016
X X X X X XXX
0 0 01 00 0 X
XX XXXX XX
XXX XXXX X
00 01 1 0 1 0
100 000 00
11 100 000
001 111 11
XXX XXXX X
X 0 XXX X X X
XXX XXXX X
X 0 XX XX X X
0 000 1 000
1
FFFD16 contents
FFFC16 contents
T
XXXX XXXX
0000 0 0 X X
01 00 1 0
0
XX
X
T The initial values depend on level of the CNV SS pin.
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