參數(shù)資料
型號(hào)： M38869MFAHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 18/111頁
文件大小： 1644K
代理商： M38869MFAHP
14
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
for flash
memory
version
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Fig. 10 Port block diagram (2)
Serial I/O1 input
(11) Port P44
Data bus
Serial I/O1 enable bit
Receive enable bit
Port latch
P4 output structure selection bit
T1
(12) Port P45
Data bus
Serial I/O1 enable bit
Transmit enable bit
Serial I/O1 output
P45/TXD P-channel output disable bit
Port latch
(13) Port P46
Serial I/O1
synchronous clock selection bit
Data bus
Serial I/O1 clock output
Serial I/O1 external clock input
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Port latch
Serial I/O1 enable bit
OBF10 output enable bit
OBF10 output
P4 output structure selection bit
(14) Port P47
(15) Port P50
(16) Ports P51,P52,P53
T1. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control
register 2 (address 002F 16).
T2. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control
register 2 (address 002F 16).
The port P8 and port P4 input register can be switched by the P8 function selection bit of the port control register 2 (address 002F16).
T3. The input level can be switched between CMOS compatible input level and TTL level by the input level selection bit of the data bus buffer
control register (address 002A 16).
(9) Port P42
OBF00 output enable bit
OBF00 output
P4 output structure selection bit
INT0 interrupt input
(10) Port P43
OBF01 output enable bit
OBF01 output
Data bus
Port latch
Direction
register
T1
P4 output structure selection bit
INT1 interrupt input
Data bus
Port latch
Data bus buffer enable bit
INT20, INT30, INT40 interrupt input
S0,R,W input
Data bus
Port latch
Data bus buffer enable bit
A0 input
Data bus buffer
enable bit
Data bus buffer
enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Data bus
Serial I/O1 ready output
Port latch
Data bus buffer function
selection bit
S1 input
T3
Data bus buffer function
selection bit
T2
Data bus
Port latch
Direction
register
T1
T2
Direction
register
Direction
register
T1
T2
T1
T2
Direction
register
Direction
register
Direction
register
T3
Direction
register
T3
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