參數(shù)資料
型號(hào)： M38869MFAHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 40/111頁(yè)
文件大?。?/td> 1644K
代理商： M38869MFAHP
34
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
for flash
memory
version
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
BUS INTERFACE
The 3886 group has a 2-byte bus interface function which is al-
most functionally equal to MELPS8-41 series and the control
signal from the host CPU side can operate it (slave mode).
It is possible to connect the 3886 group with the RD and WR
separated CPU bus directly. Figure 33 shows the block diagram of
the bus interface function.
The data bus buffer function I/O pins (P42, P43, P46, P47, P50–
P53, P8) also function as the normal digital port I/O pins. When bit
0 (data bus buffer enable bit) of the data bus buffer control regis-
ter (address 002A16) is “0,” these pins become the normal digital
port I/O pins. When it is “1,” these bits become the data bus buffer
function I/O pins.
The selection of either the single data bus buffer mode, which
uses 1 byte: data bus buffer 0 only, or the double data bus buffer
mode, which uses 2 bytes: data bus buffer 0 and data bus buffer
1, is performed by bit 1 (data bus buffer function selection bit) of
the data bus buffer control register (address 002A16). Por t P47 be-
comes S1 input in the double data bus buffer mode. When data is
written from the host CPU side, an input buffer full interrupt oc-
curs. When data is read from the host CPU, an output buffer
empty interrupt occurs. This microcomputer shares two input
buffer full interrupt requests and two output buffer empty interrupt
requests as shown in Figure 31, respectively.
Fig. 31 Interrupt request circuit of data bus buffer
Input buffer
full flag 0
IBF0
Input buffer
full flag 1
IBF1
Rising edge
detection circuit
One-shot pulse
generating circuit
One-shot pulse
generating circuit
Input buffer full interrupt
request signal IBF
Output buffer
full flag 0
OBF 0
Output buffer
full flag 1
OBF 1
One-shot pulse
generating circuit
One-shot pulse
generating circuit
Output buffer empty interrupt
request signal OBE
Interrupt request is set at this rising edge
IBF0
IBF1
IBF
OBF0
(
OBE0)
OBF1
(
OBE1)
OBE
OBE0
OBE1
Rising edge
detection circuit
Rising edge
detection circuit
Rising edge
detection circuit
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