參數(shù)資料
型號(hào)： M38869MFAHP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 55/111頁(yè)
文件大?。?/td> 1644K
代理商： M38869MFAHP
48
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
for flash
memory
version
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 001316) and “0” into the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 001616).
Set “0016” in the I2C status register (address 001416) so that
transmission/reception mode can become initializing condition.
Set a communication enable status by setting “0816” in the I2C
control register (address 001516).
Confirm the bus free condition by the BB flag of the I2C status
register (address 001416).
Set the address data of the destination of transmission in the
high-order 7 bits of the I2C data shift register (address 001216)
and set “0” in the least significant bit.
Set “F016” in the I2C status register (address 001416) to gener-
ate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
Set transmit data in the I2C data shift register (address 001216).
At this time, an SCL and an ACK clock automatically occur.
When transmitting control data of more than 1 byte, repeat step
.
Set “D016” in the I2C status register (address 001416) to gener-
ate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 001316) and “0” in the RBW bit.
Set the no ACK clock mode and SCL = 400 kHz by setting “2516”
in the I2C clock control register (address 001616).
Set “0016” in the I2C status register (address 001416) so that
transmission/reception mode can become initializing condition.
Set a communication enable status by setting “0816” in the I2C
control register (address 001516).
When a START condition is received, an address comparison is
performed.
When all transmitted addresses are “0” (general call):
AD0 of the I2C status register (address 001416) is set to “1”
and an interrupt request signal occurs.
When the transmitted addresses agree with the address set
in :
ASS of the I2C status register (address 001416) is set to “1”
and an interrupt request signal occurs.
In the cases other than the above AD0 and AAS of the I2C sta-
tus register (address 001416) are set to “0” and no interrupt
request signal occurs.
Set dummy data in the I2C data shift register (address 001216).
When receiving control data of more than 1 byte, repeat step .
When a STOP condition is detected, the communication ends.
sPrecautions when using multi-master I2C-
BUS interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I2C-BUS interface are described below.
I2C data shift register (S0: address 001216)
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
I2C address register (S0D: address 001316)
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RBW) at the above timing.
I2C status register (S1: address 001416)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
I2C control register (S1D: address 001516)
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
I2C clock control register (S2: address 001616)
The read-modify-write instruction can be executed for this regis-
ter.
I2C START/STOP condition control register (S2D: address
001716)
The read-modify-write instruction can be executed for this regis-
ter.
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