參數(shù)資料
型號(hào)： M38869MFAHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 54/111頁(yè)
文件大?。?/td> 1644K
代理商： M38869MFAHP
47
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
for flash
memory
version
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
START/STOP
condition
control register
Oscillation
frequency
f(XIN) (MHz)
Fig. 45 Address data communication format
Fig. 44 Structure of I2C START/STOP condition control register
Note: Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Main clock
divide ratio
System
clock
φ
(MHz)
SCL release time
(
s)
Setup time
(
s)
Hold time
(
s)
b7
STSP
SEL
b0
I2C START/STOP condition
control register
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
START/STOP condition generating
selection bit
0 : Setup/Hold time short mode
1 : Setup/Hold time long mode
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
(S2D : address 001716)
10
8
4
2
8
2
XXX11110
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
3.2
s (16 cycles)
3.5
s (14 cycles)
3.25
s (13 cycles)
3.0
s (3 cycles)
3.5
s (7 cycles)
3.0
s (6 cycles)
3.0
s (3 cycles)
6.2
s (31 cycles)
6.75
s (27 cycles)
6.25
s (25 cycles)
5.0
s (5 cycles)
6.5
s (13 cycles)
5.5
s (11 cycles)
5.0
s (5 cycles)
3.0
s (15 cycles)
3.25
s (13 cycles)
3.0
s (12 cycles)
2.0
s (2 cycles)
3.0
s (6 cycles)
2.5
s (5 cycles)
2.0
s (2 cycles)
5
4
1
2
1
S
Slave address
R/W
A
Data
A
Data
A/A
P
7 bits
“0”
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
A
P
7 bits
“1”
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
7 bits
“0”
8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
2nd bytes
A
Data
A
Data
A/A
P
1 to 8 bits
S
Slave address
1st 7 bits
R/W
A
7 bits
“0”
8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
Slave address
2nd bytes
A
Data
A
Sr
Slave address
1st 7 bits
R/W
A
Data
P
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
7 bits
“1”
1 to 8 bits
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