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| 型號： | M37281MKH-XXXSP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 52/172頁 |
| 文件大?。?/td> | 1319K |
| 代理商： | M37281MKH-XXXSP |
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M37281MAH
–
XXXSP,M37281MFH
–
XXXSP,M37281MKH
–
XXXSP, M37281EKSP
Rev.1.01 2003.07.16 page 52 of 170
Note:
V
REF
indicates the reference voltage (= Vcc).
Fig. 8.8.3 Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion
8.8.6 Conversion Method
Set bit 7 of the interrupt input polarity register (address 0212
16
) to
“
1
”
to generate an interrupt request at completion of A-D conver-
sion.
Set the A-D conversion
·
INT3 interrupt request bit to
“
0
”
(even
when A-D conversion is started, the A-D conversion
·
INT3 inter-
rupt reguest bit is not set to
“
0
”
automatically).
When using A-D conversion interrupt, enable interrupts by setting
A-D conversion
·
INT3 interrupt request bit to
“
1
”
and setting the
interrupt disable flag to
“
0.
”
Set the V
CC
connection selection bit to
“
1
”
to connect V
CC
to the
resistor ladder.
Select analog input pins by the analog input selection bit of the
A-D control register.
Set the A-D conversion completion bit to
“
0.
”
This write operation
starts the A-D conversion. Do not read the A-D conversion register
during the A-D conversion.
Verify the completion of the conversion by the state (
“
1
”
) of the
A-D conversion completion bit, the state (
“
1
”
) of A-D conversion
·
INT3 interrupt reguest bit, or the occurrence of an A-D conversion
interrupt.
Read the A-D conversion register to obtain the conversion results.
Note :
When the ladder resistor is disconnect from V
CC
, set the V
CC
connec-
tion selection bit to
“
0
”
between steps
and
.
8.8.7 Internal Operation
When the A-D conversion starts, the following operations are auto-
matically performed.
The A-D conversion register is set to
“
00
16
.
”
The most significant bit of the A-D conversion register becomes
“
1,
”
and the comparison voltage
“
V
ref
”
is input to the comparator.
At this point, V
ref
is compared with the analog input voltage
“
V
IN
.
”
Bit 7 is determined by the comparison results as follows.
When V
ref
< V
IN
: bit 7 holds
“
1
”
When V
ref
> V
IN
: bit 7 becomes
“
0
”
With the above operations, the analog value is converted into a digi-
tal value. The A-D conversion terminates in a maximum of 50 ma-
chine cycles (12.5
μ
s at f(X
IN
) = 8 MHz) after it starts, and the con-
version result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time as A-D
conversion completion, the A-D conversion
·
INT3 interrupt request
bit becomes
“
1.
”
The A-D conversion completion bit also becomes
“
1.
”
Table 8.8.1 Expression for V
ref
and V
REF
A-D conversion register contents
“
n
”
(decimal notation)
0
1 to 255
Vref (V)
0
V
REF
2
V
REF
2
V
REF
2
V
REF
512
V
REF
4
V
REF
4
V
REF
512
V
REF
8
V
REF
512
V
REF
2
V
REF
4
V
REF
8
V
REF
256
V
REF
512
1 2
3 4 5 6
Digital value corresponding to
analog input voltage.
7 8
1 0 0 0 0
0 0
0
1 2
1 0 0
0 0
0
1 0 0 0
0 0
0
1
1 2
3 4 5
6
7
1
–
–
±
–
±
±
0 0 0 0 0
0 0 0
Contents of A-D conversion register
Reference voltage (V
ref
)
[V]
0
A-D conversion start
1st comparison start
3rd comparison start
8th comparison start
2nd comparison start
A-D conversion completion
(8th comparison completion)
±
±
±
–
±
.......
: Value determined by mth (m = 1 to 8) result
m
.....
V
REF
256
(n
–
0.5)
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