參數(shù)資料
型號： M37281MKH-XXXSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 40/172頁
文件大?。?/td> 1319K
代理商： M37281MKH-XXXSP
M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Rev.1.01 2003.07.16 page 40 of 170
(8) Bit 7: Communication Mode Specification Bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when
arbitration lost is detected
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
At reset
Fig. 8.6.7 I
2
C Status Register
b7 b
6 b
5 b
4 b
3 b
2 b
1 b0
I
2
C status register (S1) [Address 00F8
16
]
I
2
C
S
t
a
t
u
s
R
e
g
i
s
t
e
r
0
3
4
5
6, 7
b7 b6
0 0 : Slave recieve mode
0 1 : Slave transmit mode
1 0 : Master recieve mode
1 1 : Master transmit mode
1
2
0
0
0
1
0
B
Name
Functions
A
f
In
t
e
r
r
e
s
e
t
R W
C
s
(
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R
m
i
f
X
u
c
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n
T
t
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o
b
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t
m
s
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d
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c
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t
)
0 : Bus free
1 : Bus busy
B
u
s
b
u
s
y
f
l
a
g
(
B
B
)
0 : Interrupt request issued
1 : No interrupt request issued
I
2
C
r
e
-
u
B
e
U
s
S
t
i
i
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t
t
(
e
P
r
f
I
a
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)
e
i
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t
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r
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u
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t
q
b
0 : Not detected
1 : Detected
A
(
A
r
b
L
i
)
t
r
(
a
S
t
i
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o
n
n
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)
d
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c
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g
f
l
a
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e
0 : Address mismatch
1 : Address match
S
f
l
l
a
g
v
e
(
a
A
d
S
d
r
e
(
s
S
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e
c
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n
m
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p
t
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a
)
r
i
s
o
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a
A
)
0 : No general call detected
1 : General call detected
G
(
A
e
n
e
0
r
)
a
(
l
S
c
e
a
e
l
l
n
d
o
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t
t
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e
)
c
t
i
n
g
f
l
a
g
D
0 : Last bit =
“
0
”
1 : Last bit =
“
1
”
L
(
a
S
s
e
t
e
r
e
n
c
o
e
t
e
i
v
)
e
b
i
t
(
L
R
B
)
N
o
t
e
:
T
h
e
s
e
b
i
t
s
a
n
d
f
l
a
g
s
c
a
n
b
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e
a
d
o
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t
,
b
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a
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n
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b
e
w
r
i
t
t
e
n
.
d
e
t
e
r
m
i
n
a
t
e
R
—
R
—
R
—
R
—
R W
R W
0
R W
(S
e
e
n
o
t
e
)
(S
e
e
n
o
t
e
)
(S
e
e
n
o
t
e
)
(S
e
e
n
o
t
e
)
Fig. 8.6.8 Interrupt Request Signal Generation Timing
SCL
PIN
IICIRQ
Note:
The START condition duplication prevention function disables the START
condition generation, reset of bit counter reset, and SCL output, when
the following condition is satisfied:
a START condition is set by another master device.
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