參數(shù)資料
型號(hào)： M37281MKH-XXXSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 23/172頁
文件大?。?/td> 1319K
代理商： M37281MKH-XXXSP
Rev.1.01 2003.07.16 page 23 of 170
M37281MAH
–
XXXSP,M37281MFH
–
XXXSP,M37281MKH
–
XXXSP, M37281EKSP
Fig. 8.3.2 Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC
B
0
Name
Interrupt Request Register 1
Timer 1 interrupt
request bit (TM1R)
Timer 2 interrupt
request bit (TM2R)
Timer 3 interrupt
request bit (TM3R)
Timer 4 interrupt
request bit (TM4R)
OSD interrupt request
bit (OSDR)
V
SYNC
interrupt
request bit (VSCR)
A-D conversion
INT3
external interrupt request
bit (ADR)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is
“
0.
”
1
2
3
4
5
6
7
:
“
0
”
can be set by software, but
“
1
”
cannot be set.
16
]
Functions
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
After reset
R W
0
0
0
0
0
0
0
—
R
R
R
R
R
R
R
R
0
Fig. 8.3.3 Interrupt Request Register 2
b7 b6b5b4b3 b2b1b0
0
Interrupt request register 2 (IREQ2) [Address 00FD
B
0
Name
Interrupt Request Register 2
INT1 external interrupt
request bit (IN1R)
Data slicer interrupt
request bit (DSR)
Serial I/O interrupt
request bit (SIOR)
f(X
IN
)/4096
SPRITE OSD
interrupt request bit (CKR)
1
2
3
4
INT2 external interrupt request
bit (IN2R)
Multi-master I
2
C-BUS interrupt
request bit (IICR)
Timer 5
6 interrupt
request bit (TM56R)
5
7
Fix this bit to
“
0.
”
:
“
0
”
can be set by software, but
“
1
”
cannot be set.
16
]
6
Functions
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
After reset
0
0
0
0
0
0
0
0
R W
R
R
R
R
R
R
R W
R
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