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| 型號(hào)： | M37281MKH-XXXSP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁(yè)數(shù)： | 22/172頁(yè) |
| 文件大?。?/td> | 1319K |
| 代理商： | M37281MKH-XXXSP |
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M37281MAH
–
XXXSP,M37281MFH
–
XXXSP,M37281MKH
–
XXXSP, M37281EKSP
Rev.1.01 2003.07.16 page 22 of 170
(4) Serial I/O Interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
(5) f(X
IN
)/4096 SPRITE OSD Interrupt
The f (X
IN
)/4096 interrupt occurs regularly with a f(X
IN
)/4096 pe-
riod. Set bit 0 of the PWM mode register 1 to
“
0.
”
The SPRITE OSD interrupt occurs at the completion of SPRITE
display.
Since f(X
IN
)/4096 interrupt and SPRITE OSD interrupt share the
same vector, an interrupt source is selected by bit 5 of the SPRITE
OSD control register (address 0258
16
).
(6) Data Slicer Interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I
2
C-BUS Interface Interrupt
This is an interrupt request related to the multi-master I
2
C-BUS
interface.
(8) A-D Conversion INT3 external Interrupt
The A-D conversion interrupt occurs at the completion of A-D
conversion.
The INT3 is an external input,the system detects that the level of
a pin changes from LOW to HIGH or from HIGH to LOW, and
generates an interrupt request. The input active edge can be
selected by bit 6 of the interrupt input polarity register (address
0212
16
) : when this bit is
“
0,
”
a change from LOW to HIGH is
detected; when it is
“
1,
”
a change from HIGH to LOW is detected.
Note that this bit is cleared to
“
0
”
at reset.
Since A-D conversion interrupt and the INT3 external interrupt
share the same vector, an interrupt source is selected by bit 7 of
the interrupt interval determination control register (address
0212
16
).
(9) Timer 5 6 Interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(10) BRK Instruction Interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Fig. 8.3.1 Interrupt Control
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt
request
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