參數(shù)資料
型號： M34552M8H-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù)： 142/143頁
文件大?。?/td> 0K
代理商： M34552M8H-XXXFP
8: REGISTERS
1-86
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
Display Conguration Registers
bit 7
SwivelViewTM Enable
When this bit = 1, all CPU accesses to the display buffer are translated to provide clock-
wise 90 hardware rotation of the display image. Refer to Section 13, “SwivelViewTM”
for application and limitations.
bits 6–5
Simultaneous Display Option Select Bits [1:0]
These bits are used to select one of four different simultaneous display mode options:
Normal, Line Doubling, Interlace, or Even Scan Only. The purpose of these modes is to
manipulate the vertical resolution of the image so that it ts on both the CRT, typically
640x480, and LCD. The following table describes the four modes using a 640x480 CRT
as an example:
Notes: 1. Dual Panel Considerations:
When configured for a dual LCD panel and using Simultaneous Display, the Half Frame Buffer
Disable, REG[1Bh] bit 0, must be set to 1.
This results in a lower contrast on the LCD panel, which may require adjustment.
2. The Line doubling option is not supported with dual panel.
Display Mode Register
REG[0Dh]
RW
SwivelViewTM
Enable
Simultaneous
Display Option
Select Bit 1
Simultaneous
Display Option
Select Bit 0
Bit-per-pixel
Select Bit 2
Bit-per-pixel
Select Bit 1
Bit-per-pixel
Select Bit 0
CRT Enable
LCD Enable
Table 8-6 Simultaneous Display Option Selection
Simultaneous
Display Option
Select Bits [1:0]
Simultaneous
Display Mode
Mode Description
00
Normal
The image is not manipulated. This mode is used when the CRT and LCD have the same reso-
lution, e.g. 480 lines.
It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD duty
cycle
(1/525 compared to the usual 1/481). This reduced duty cycle may result in lower con-
trast on the LCD.
01
Line Doubling
Each line is replicated on the CRT. This mode is used to display a 240-line image on a 240-line
LCD and stretch it to a 480-line image on the CRT. The CRT has a heightened aspect ratio.
It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD duty
cycle
(2/525 compared to the usual 1/241). This reduced duty cycle is not extreme and the con-
trast of the LCD image should not be greatly reduced.
10
Interlace
The odd and even elds of a 480-line image are interlaced on the LCD. This mode is used to
display a 480-line image on the CRT and squash it onto a 240-line LCD. The full image is
viewed on the LCD but the interlacing may create icker. The LCD has a shortened aspect
ratio.
It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD duty
cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme and the con-
trast of the LCD image should not be greatly reduced.
11
Even Scan Only
Only the even eld of a 480-line image is displayed on the LCD. This is an alternate method to
display a 480-line image on the CRT and squash it onto a 240-line LCD. Only the even scans
are viewed on the LCD. The LCD has a shortened aspect ratio.
It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD duty
cycle
(2/525 compared to the usual 1/241). This reduced duty cycle is not extreme and the con-
trast of the LCD image should not be greatly reduced.
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