參數(shù)資料
型號: M34552M8H-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù): 140/143頁
文件大小: 0K
代理商: M34552M8H-XXXFP
8: REGISTERS
1-84
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
bit 7
Vertical Non-Display Period Status
This is a read-only status bit.
When this bit = 1, a vertical non-display period is indicated.
When this bit = 0, a vertical display period is indicated.
bits 5–0
Vertical Non-Display Period Bits [5:0]
These bits specify the vertical non-display period.
Vertical non-display period (lines) = Vertical Non-Display Period Bits [5:0]
Note: This register must be programmed such that
REG[0Ah]
≥ 1 and (REG[0Ah] bits [5:0] + 1) ≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
bits 5–0
VRTC/FPFRAME Start Position Bits [5:0]
For CRT and TFT/D-TFD, these bits specify the delay in lines from the start of the verti-
cal non-display period to the leading edge of the VRTC pulse and FPFRAME pulse
respectively. For passive LCD, FPFRAME is automatically created and these bits have no
effect.
VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1
The maximum start delay is 64 lines.
Note: This register must be programmed such that
(REG[0Ah] bits [5:0] + 1)
≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
For exact timing please use the timing diagrams in section 7.5
Vertical Non-Display Period Register
REG[0Ah]
RW
Vertical Non-
Display Period
Status (RO)
n/a
Vertical Non-
Display Period
Bit 5
Vertical Non-
Display Period
Bit 4
Vertical Non-
Display Period
Bit 3
Vertical Non-
Display Period
Bit 2
Vertical Non-
Display Period
Bit 1
Vertical Non-
Display Period
Bit 0
VRTC/FPFRAME Start Position Register
REG[0Bh]
RW
n/a
VRTC/
FPFRAME
Start Position
Bit 5
VRTC/
FPFRAME
Start Position
Bit 4
VRTC/
FPFRAME
Start Position
Bit 3
VRTC/
FPFRAME
Start Position
Bit 2
VRTC/
FPFRAME
Start Position
Bit 1
VRTC/
FPFRAME
Start Position
Bit 0
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