參數(shù)資料
型號(hào)： M34552M8H-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù)： 136/143頁
文件大小： 0K
代理商： M34552M8H-XXXFP
8: REGISTERS
1-80
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
8.2 Register Descriptions
Unless specied otherwise, all register bits are reset to 0 during power up. Reserved bits should be
written 0 when programming unless otherwise noted.
Revision Code Register
bits 7–2
Product Code Bits [5:0]
This is a read-only register that indicates the product code of the chip.
The product code for the S1D13505F00A is 000011.
bits 1–0
Revision Code Bits [1:0]
This is a read-only register that indicates the revision code of the chip.
The revision code for the S1D13505F00A is 00.
Memory Conguration Registers
bits 6–4
DRAM Refresh Rate Select Bits [2:0]
These bits specify the divisor used to generate the DRAM refresh rate from the input
clock (CLKI).
bit 2
WE# Control
When this bit = 1, 2-WE# DRAM is selected.
When this bit = 0, 2-CAS# DRAM is selected.
bit 0
Memory Type
When this bit = 1, FPM-DRAM is selected.
When this bit = 0, EDO-DRAM is selected.
This bit should be changed only when there are no read/write DRAM cycles. This condi-
tion occurs when all of the following are true: the Display FIFO is disabled (REG[23h]
bit 7 = 1), and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1), and the Ink/Cursor
is inactive(Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD
enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset. For further program-
ming information, see “S1D13505 Programming Notes and Examples”, document num-
ber X23A-G-003-05.
Revision Code Register
REG[00h]
RO
Product Code
Bit 5
Product Code
Bit 4
Product Code
Bit 3
Product Code
Bit 2
Product Code
Bit 1
Product Code
Bit 0
Revision Code
Bit 1
Revision Code
Bit 0
Memory Conguration Register
REG[01h]
RW
n/a
Refresh Rate
Bit 2
Refresh Rate
Bit 1
Refresh Rate
Bit 0
n/a
WE# Control
n/a
Memory Type
Table 8-2 DRAM Refresh Rate Selection
DRAM Refresh Rate
Select Bits [2:0]
CLKI Frequency
Divisor
Example Refresh Rate
for CLKI = 33MHz
Example period for
256 refresh cycles at
CLKI = 33MHz
000
64
520 kHz
0.5 ms
001
128
260 kHz
1 ms
010
256
130 kHz
2 ms
011
512
65 kHz
4 ms
100
1024
33 kHz
8 ms
101
2048
16 kHz
16 ms
110
4096
8 kHz
32 ms
111
8192
4 kHz
64 ms
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