參數(shù)資料
型號: M28W800B100N1T
廠商: NUMONYX
元件分類: PROM
英文描述: 512K X 16 FLASH 3V PROM, 100 ns, PDSO48
封裝: 12 X 20 MM, PLASTIC, TSOP-48
文件頁數(shù): 39/40頁
文件大?。?/td> 284K
代理商: M28W800B100N1T
M28W800T, M28W800B
8/40
Erasing should not be attempted when VPP is not
within the allowed range of values (VDD or VPPH)
as the results will be uncertain. Status Register bit
b3 returns a ’1’ if VPP is not within the allowed
range of values when erasing is attempted and/or
during erasing execution. Refer to the signals de-
scription section for details of the allowable rang-
es.
Erase aborts if VPP drops out of the allowed range
or RP turns to VIL. As data integrity cannot be
guaranteed when the erase operation is aborted,
the erase must be repeated. A Clear Status Reg-
ister instruction must be issued to reset b3 of the
Status Register.
During the execution of the erase by the P/E.C.,
the memory accepts only the RSR (Read Status
Register) and PES (Program/Erase Suspend) in-
structions.
Table 8. Instructions
Note: 1. X = Don’t Care.
2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations to read memory array, Status Register or
Electronic Signature codes. Any number of Read cycle can occur after one command cycle.
3. Signature address bit A0=VIL will output Manufacturer code. Address bit A0=VIH will output Device code. Other address bits are
ignored.
Mne-
monic
Instruction
Cycles
1st Cycle
2nd Cycle
Operation
Address (1)
Data
Operation
Address
Data
RD
Read Memory
Array
1+
Write
X
FFh
Read (2)
Read
Address
Data
RSR
Read Status
Register
1+
Write
X
70h
Read (2)
X
Status
Register
RSIG
Read
Electronic
Signature
1++
Write
X
90h
Read (2)
Signature
Address (3)
Signature
RCFI
CFI Query
1+
Write
X
98h
Read (2)
CFI Address
Query
RDO
Read OTP
Area
1+
Write
X
80h
Read (2)
OTP
Address
OTP Data
EE
Erase
2
Write
X
20h
Write
Block
Address
D0h
PG
Program
2
Write
X
40h or 10h
Write
Address
Data Input
PDO
Program OTP
Area
2
Write
X
30h
Write
OTP
Address
OTP Data
Input
CLRS
Clear Status
Register
1
Write
X
50h
PES
Program/Erase
Suspend
1
Write
X
B0h
PER
Program/Erase
Resume
1
Write
X
D0h
Erase (EE)
Block erasure sets all the bits within the selected
block to ’1’. One block at a time can be erased. It
is not necessary to program the block with 00h as
the P/E.C. will do it automatically before erasing.
This instruction uses two write cycles. The first
command written is the Erase Set up command
20h. The second command is the Erase Confirm
command D0h. An address within the block to be
erased is given and latched into the memory dur-
ing the input of the second command. If the sec-
ond command given is not an erase confirm, the
status register bits b4 and b5 are set and the in-
struction aborts.
Read operations output the status register after
erasure has started.
Status Register bit b7 returns ’0’ while the erasure
is in progress and ’1’ when it has completed. After
completion the Status Register bit b5 returns ’1’ if
there has been an Erase Failure.
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