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M28W800T, M28W800B
10/40
Program (PG)
The memory array can be programmed word-by-
word. This instruction uses two write cycles. The
first command written is the Program Set-up com-
mand 40h (or 10h). A second write operation latch-
es the Address and the Data to be written and
starts the P/E.C.
Read operations output the Status Register con-
tent after the programming has started. The Status
Register bit b7 returns ’0’ while the programming is
in progress and ’1’ when it has completed. After
completion the Status register bit b4 returns ’1’ if
there has been a Program Failure. Programming
should not be attempted when VPP is not within the
allowed range of values (VDD or VPPH) as the re-
sults will be uncertain. Status Register bit b3 re-
turns a ’1’ if VPP is not within the allowed range of
values when programming is attempted and/or
during programming execution. Refer to the sig-
nals description section for details.
Programming aborts if VPP drops out of the al-
lowed range or RP goes to VIL. As data integrity
cannot be guaranteed when the program opera-
tion is aborted, the memory location must be
erased and re-programmed. A Clear Status Regis-
ter instruction must be issued to reset b3 of the
Status Register.
During the execution of the program by the P/E.C.,
the memory accepts only the RSR (Read Status
Register) and PES (Program/Erase Suspend) in-
structions.
Program OTP Area (PDO)
The Program OTP Area (PDO) instruction is a two
write cycle instruction: the first code issues is the
OTP Program Setup command 30h, while during
the second write cycle the OTP selected Address
and the OTP Data to be written are applied to the
device. The conventional Read Status Register
operation can be performed to monitor the end of
the programming operation. To return in the Read
Memory Array mode write the Read command
FFh.
Clear Status Register (CLRS)
The Clear Status Register uses a single write op-
eration which clears bits b3, b4 and b5 to ’0’. Its
use is necessary before any new operation when
an error has been detected.
Note, also, that the Read Array command must be
issued before data can be read from the memory
array. The Clear Status Register is executed writ-
ing the command 50h.
Program/Erase Suspend (PES)
As Erase takes in the order of seconds to com-
plete, a Program/Erase Suspend instruction is
provided. Program/Erase Suspend interrupts the
Program/Erase routine allowing read from and
program to data belonging to a different block.
Program/Erase suspend is accepted only during
the Program/Block Erase instruction execution.
When a Program/Erase Suspend command is
written to the C.I., the P/E.C. freezes the Program/
Erase operation. Program/Erase Resume (PER)
continues the Program/Erase operation.
Program/Erase Suspend consists of writing the
command B0h without any specific address.
The Status Register bit b2 is set to ’1’ when the
program has been suspended. b2 is set to ’0’ in
case the program is completed or in progress.
The Status Register bit b6 is set to ’1’ when the
erase has been suspended. b6 is set to ’0’ in case
the erase is completed or in progress.
The valid commands while erase is suspended are
Program/Erase Resume, Program, Read Array,
Read Status Register, Read Identifier, CFI Query.
While program is suspended the same command
set is valid except for program instruction. During
program/erase suspend mode, the chip can be
placed in a pseudo-standby mode by taking E to
VIH. This reduces active current consumption.
VPP must be maintained within the allowed range
of values (VDD or VPPH) while program/erase is
suspended. Program/Erase is aborted if VPP
drops out of the allowed range or RP turns to VIL
and Status Register b5 and b3 are set.
Program/Erase Resume (PER)
If a Program/Erase Suspend instruction was previ-
ously executed, the program/erase operation may
be resumed by issuing the command D0h.
The status register bit b2/b6 is cleared when pro-
gram/erase resumes. Read operations output the
status register after the program/erase is re-
sumed.
The suggested flow charts for programs that use
the programming, erasure and program/erase
suspend/resume features of the memories are
shown from Figures 9, 10, 11 and 12.