參數(shù)資料
型號: M28W800B100N1T
廠商: NUMONYX
元件分類: PROM
英文描述: 512K X 16 FLASH 3V PROM, 100 ns, PDSO48
封裝: 12 X 20 MM, PLASTIC, TSOP-48
文件頁數(shù): 36/40頁
文件大?。?/td> 284K
代理商: M28W800B100N1T
5/40
M28W800T, M28W800B
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A18). The address signals
are inputs driven with CMOS voltage levels. They
are latched during a write operation.
Data Input/Output (DQ0-DQ15). The
data
in-
puts, a word to be programmed or a command to
the C.I., are latched on the Chip Enable E or Write
Enable W rising edge, whichever occurs first. The
data output from the memory Array, the Electronic
Signature or Status Register is valid when Chip
Enable E and Output Enable G are active. The
output is high impedance when the chip is dese-
lected, the outputs are disabled or RP is tied to VIL.
Commands are issued on DQ0-DQ7.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at VIH deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at VIL.
Output Enable (G). The Output Enable controls
the data Input/Output buffers.
Write Enable (W). This input controls writing to
the Command Register, Input Address and Data
latches.
Write Protect (WP). Write Protect is an input to
protect or unprotect the two lockable parameter
blocks. When WP is at VIL, the lockable blocks are
protected. Program or erase operations are not
achievable. When WP is at VIH, the lockable
blocks are unprotected and they can be pro-
grammed or erased (refer to Table 9).
Reset/Power Down Input (RP). The
RP
input
provides hardware reset of the memory and power
down functions. When RP is at VIL, the memory is
in reset/deep power down mode. The outputs are
put to High-Z and the current consumption is min-
imised. When RP is at VIH, the device is in normal
operation. Exiting reset/deep power down mode
the device enters read array mode.
VDD Supply Voltage (2.7V to 3.6V). VDD
pro-
vides the power supply to the internal core of the
memory device. It is the main power supply for all
operations (Read, Program and Erase). It ranges
from 2.7V to 3.6V.
VDDQ Supply Voltage (1.65V to VDD+0.3V).
VDDQ provides the power supply to the I/O pins
and enables all Outputs to be powered indepen-
dently from VDD. VDDQ can be tied to VDD or it can
use a separate supply. It can be powered either
from 1.65V to 2.2V or from 2.7V to 3.6V.
VPP Program Supply Voltage (12V). VPP is the
power supply for program and erase operations.
The M28W800 is intended to execute program
and erase operations at VDD voltage ranges. Nev-
ertheless, customers wishing to speed up pro-
gramming at their manufacturing environment can
also apply 12V to VPP. This is not intended for ex-
tended use.
VPP can be connected to 12V for a total of 80
hours maximum. 12V may be applied to VPP dur-
ing program and erase for 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks.
Stressing the device beyond these limits could
damage the device.
VPP may be tied to 5V during read or idle phases.
5V supply is forbidden for program or erase oper-
ations. The VPP must be supplied with either 2.7V
to 3.6V or 11.4V to 12.6V during programming or
erase operations. VPP can be tied to VSS to
achieve a complete block protection.
VSS Ground. VSS is the reference for all the volt-
age measurements.
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