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參數(shù)資料
| 型號： | M12L2561616A |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 4米× 16位× 4個銀行同步DRAM |
| 文件頁數(shù)： | 12/44頁 |
| 文件大小： | 908K |
| 代理商： | M12L2561616A |
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ES MT
DEVICE OPERATIONS (Continued)
AUTO REFRESH
M12L2561616A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
Publication Date
:
Aug. 2007
12/44
The storage cells of SDRAM need to be refreshed every 64ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the
rows. An auto refresh command is issued by asserting low on
CS , RAS and CAS with high on CKE and
WE
. The auto
refresh command can only be asserted with all banks being in
idle state and the device is not in power down mode (CKE is
high in the previous cycle). The time required to complete the
auto refresh operation is specified by t
RFC(min)
. The minimum
number of clock cycles required can be calculated by driving
t
RFC
with clock cycle time and them rounding up to the next
higher integer. The auto refresh command must be followed by
NOP’s until the auto refresh operation is completed. The auto
refresh is the preferred refresh mode when the SDRAM is
being used for normal data transactions. The auto refresh
cycle can be performed once in 7.8us.
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
The self refresh mode is entered from all banks idle state
by asserting low on CS , RAS , CAS and CKE with
high on
WE
. Once the self refresh mode is entered, only
CKE state being low matters, all the other inputs including
clock are ignored to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of t
RFC
before the SDRAM
reaches idle state to begin normal operation. It is
recommended to use burst 8192 auto refresh cycles
immediately before and after self refresh.
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| M12L2561616A-6BG | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A-6TG | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A-7BG | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A-7TG | 4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L32162A | 1M x 16Bit x 2Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L2561616A_08 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A2K | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply |
| M12L2561616A-5BG2K | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply |
| M12L2561616A-5TG2K | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply |
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