參數(shù)資料
型號: M12L128324A-6BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90
封裝: 13 X 8 MM, LEAD FREE, FBGA-90
文件頁數(shù): 6/47頁
文件大?。?/td> 794K
代理商: M12L128324A-6BG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
6/47
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
C
° , f = 1MHZ)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A10, BA0 ~ BA1)
CIN1
2
4
pF
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
& DQM)
CIN2
2
4
pF
Data input/output capacitance (DQ0 ~ DQ31)
COUT
2
5
pF
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted
,
T
A
= 0 to 70°
Version
Parameter
Symbol
Test Condition
CAS
Latency
-6
-7
Unit
Note
Operating Current
(One Bank Active)
I
CC1
Burst Length = 1
t
RC
t
RC(min)
I
OL
= 0 mA
120
100
mA
1,2
I
CC2P
CKE
V
IL
(max), tcc = 10ns
2
Precharge Standby Current
in power-down mode
I
CC2PS
CKE & CLK
V
IL
(max), t
cc
=
1
mA
I
CC2N
CKE
V
IH
(min), CS
V
IH
(min), t
cc
= 10ns
Input signals are changed one time during 20ns
25
Precharge Standby Current
in non power-down mode
I
CC2NS
CKE
V
IH
(min), CLK
V
IL
(max), t
cc
=
input signals are stable
9
mA
I
CC3P
CKE
V
IL
(max), tcc = 10ns
7
Active Standby Current
in power-down mode
I
CC3PS
CKE & CLK
V
IL
(max), t
cc
=
6
mA
I
CC3N
CKE
VIH(min), CS
V
IH
(min), tcc = 15ns
Input signals are changed one time during 30ns
30
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3NS
CKE
V
IH
(min), CLK
V
IL
(max), tcc =
input signals are stable
15
mA
Operating Current
(Burst Mode)
I
CC4
IOL = 0 mA
Page Burst
2 Banks activated
t
CK
= t
CK(min)
270
240
mA
1,2
Refresh Current
Self Refresh Current
I
CC5
I
CC6
t
RC
t
RC(min)
CKE
0.2V
270
240
mA
mA
2
Note : 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
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