參數(shù)資料
型號: M12L128324A-6BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90
封裝: 13 X 8 MM, LEAD FREE, FBGA-90
文件頁數(shù): 20/47頁
文件大?。?/td> 794K
代理商: M12L128324A-6BG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
20/47
3.
CAS
Interrupt (I)
*Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write.
2. t
CCD
:CAS to CAS delay. (=1CLK)
3. t
CDL
: Last data in to new column address delay. (=1CLK)
CLK
C M D
AD D
DQ( CL2)
DQ(CL3)
R D
QB0
QB2
QA0
CLK
C M D
AD D
DQ
W R
DA0
DB0
DB1
R D
A
B
QB1
QB3
QB0
QB2
QA0
QB3
QB1
t
CC D
*N ot e 2
W R
t
C CD *N o t e 2
A
B
t
CD L
*N ot e 3
W R
R D
t
C CD *N o t e 2
A
B
DA0
DQ0
DQ1
t
CD L
*N ot e 3
DA0
DQ0
DQ1
DQ( CL3)
DQ( CL2)
1) R ea d in t er ru p t ed b y R ead ( B L = 4 )
2) W r it e in t e r r u p t ed b y W r it e (B L = 2 )
3) W r i t e i n t e rr u p t ed b y R e ad ( B L= 2 )
*Not e 1
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