參數(shù)資料
型號: M12L128324A-6BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90
封裝: 13 X 8 MM, LEAD FREE, FBGA-90
文件頁數(shù): 34/47頁
文件大?。?/td> 794K
代理商: M12L128324A-6BG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
34/47
Page Read & Write Cycle at Same Bank @ Burst Length = 4
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input , t
RDL
before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
0 1 2 3
4 5 6
7
8
9
10
11
12
13
14 15 16 17
18
19
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
BA1
BA0
CL =2
CL =3
*Not e 3
Row Active
( A - Bank )
Read
( A - Bank )
Read
( A - Bank )
Write
( A - Bank )
Write
( A - Bank )
Precharge
(A - Bank)
: D o n ' t C a r e
Qa0
Qa1
Qb0
Qb1
Dd0
Dd1
t
CD L
Dc1
Dc0
Qa1
Qb0
Qb1
Qb2
Dc1
Dd0
Dd1
Dc0
Qa0
Ra
C c
Cd
Ra
Ca
Cb
*Not e 1
HIGH
t
RC D
t
RD L
* Not e 2
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