- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377800 > M12L128324A-6BG (ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC) 1M x 32 Bit x 4 Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | M12L128324A-6BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90 |
| 封裝： | 13 X 8 MM, LEAD FREE, FBGA-90 |
| 文件頁數(shù)： | 26/47頁 |
| 文件大?。?/td> | 794K |
| 代理商： | M12L128324A-6BG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
26/47
12. About Burst Type Control
Sequential Counting
Interleave Counting
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Basic
MODE
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Random
MODE
Random Column Access
t
CCD
= 1 CLK
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
1
At MRS A210 = “000”
At auto precharge . tRAS should not be violated.
2
At MRS A210 = “001”
At auto precharge . tRAS should not be violated.
4
At MRS A210 = “010”
8
At MRS A210 = “011”
Basic
MODE
Full Page
At MRS A210 = “111”
At the end of the burst length , burst is warp-around.
Random
MODE
Burst Stop
t
BDL
= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
RAS Interrupt
(Interrupted by
Precharge)
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
t
RDL
= 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Interrupt
MODE
CAS Interrupt
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12L128324A-6TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L16161A-5TG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7BG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7TG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12L2561616A | 4M x 16 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L128324A-6BG2E | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply |
| M12L128324A-6BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。