參數(shù)資料
型號: M12L128324A-6BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90
封裝: 13 X 8 MM, LEAD FREE, FBGA-90
文件頁數(shù): 36/47頁
文件大?。?/td> 794K
代理商: M12L128324A-6BG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
36/47
Page Write Cycle at Different Bank @ Burst Length = 4
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
BA1
BA0
: D o n ' t c a r e
*Not e 1
RAa
RBb
CAa
CBb
RD d
C C c
R C c
CD d
*Not e 2
DAa1
DAa0
DBb0 DBb1
DBb3
DDd0 DDd1
DAa2
DBb2
DCc0 DCc1
RAa
RBb
R C c
RD d
DAa3
CDd2
t
CD L
R o w A c t i v e
( A - Bank )
R o w A c t i v e
( B - B a n k )
W r i t e
( A - B a n k )
W r i t e
( B - B a n k )
R o w A c t i v e
( C - B a n k )
W r i t e
( C - B a n k )
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
( D - B a n k )
W r i t e
( D - B a n k )
HIGH
t
RD L
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