參數(shù)資料
型號: LXT384BE
元件分類: 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 65/80頁
文件大?。?/td> 1112K
代理商: LXT384BE
Octal T1/E1/J1 Transceiver
LXT384
Datasheet
65
Table 48. Intel Mode Write Timing Characteristics
2
Parameter
Sym
Min.
Typ
1
Max
Unit
Test Conditions
Address setup time to latch
Tsalw
10
ns
Valid address latch pulse width
Tvl
30
ns
Latch active to active write setup time
Tslw
10
ns
Chip select setup time to active write
Tscsw
0
ns
Chip select hold time from inactive write
Thcsw
0
ns
Address hold time from inactive ALE
Thalw
5
ns
Data valid to write active setup time
Tsdw
40
ns
Data hold time to active write
Thdw
30
ns
Address setup time to WR inactive
Thaw
2
ns
Address hold time from WR inactive
Tsaw
6
ns
Valid write signal pulse width
Tvwr
60
ns
Inactive write to inactive INT delay time
Tint
10
ns
Chip select to RDY delay time
3
Tdrdy
0
12
ns
Active ready Low time
Tvrdy
40
ns
Inactive ready to tri-state delay time
3
Trdyz
3
ns
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production
testing.
2. C
= 100pF on D0-D7, all other outputs are loaded with 50pF.
3. These times don't apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please
refer to Reset Operation and Host Mode sections for more information.
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