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參數(shù)資料
| 型號： | LXT384BE |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 19/80頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT384BE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
19
84
84
84
84
J14
J14
J14
J14
DS
WR
SDI
LEN0
DI
DI
DI
DI
Data Strobe Input (Motorola Mode).
Write Enable Input (Intel mode).
Serial Data Input (Serial Mode).
Line Length Equalizer Input (Hardware Mode).
Host Mode
This pin acts as data strobe in Motorola mode and as Write Enable in
Intel mode. In serial mode, this pin is used as Serial Data Input.
Hardware Mode
This pin determines the shape and amplitude of the transmit pulse.
Please refer to
Table 2
.
85
85
85
J13
J13
J13
R/W
RD
LEN1
DI
DI
DI
Read/Write Input (Motorola Mode).
Read Enable Input (Intel Mode).
Line Length Equalizer Input (Hardware Mode).
Host Mode
This pin functions as the read/write signal in Motorola mode and as the
Read Enable in Intel mode.
Hardware Mode
This pin determines the shape and amplitude of the transmit pulse.
Please refer to
Table 2
.
86
86
86
86
J12
J12
J12
J12
ALE
SCLK
AS
LEN2
DI
DI
DI
DI
Address Latch Enable Input.
Shift Clock Input (Serial Mode).
Address Strobe (Motorola Mode).
Line Length Equalizer Input (Hardware Mode).
Host Mode
The address on the multiplexed address/data bus is clocked into the
device with the falling edge of ALE.
In serial Host mode, this pin acts as serial shift clock.
In Motorola mode, this pin acts a active Low address strobe.
Hardware Mode
This pin determines the shape and amplitude of the transmit pulse.
Please refer to
Table 2
.
87
87
J11
J11
CS
JASEL
DI
Chip Select/Jitter Attenuator Select Input
.
Host Mode
This active Low input is used to access the serial/parallel interface. For
each read or write operation, CS must transition from High to Low, and
remain Low.
Hardware Mode
This input determines the Jitter Attenuator position:
Table 1. LXT384 Pin Description (Sheet 9 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
JASEL
JA Position
L
Transmit Path
H
Receive Path
Z
Disabled
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT384LE | Telecomm/Datacomm |
| LXT386BE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT388LE | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT400JE | Hermetically Sealed, 3.3V, High Speed, High CMR, Logic Gate Optocoupler |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT384LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT386 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:QUAD T1/E1/J1 Transceiver |
| LXT386BE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | 制造商:LEVEL1 功能描述: |
| LXT388LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
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