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參數(shù)資料
| 型號(hào)： | LXT384BE |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 11/80頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT384BE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
11
Table 1. LXT384 Pin Description (Sheet 1 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1
1
B2
B2
TPOS7
TDATA7
DI
DI
Transmit Positive Data Input.
Transmit Data Input.
2
B1
TCLK7
DI
Transmit Clock Input.
During normal operation TCLK is active, and
TPOS and TNEG are sampled on the falling edge of TCLK.
If TCLK is
Low, the output drivers enter a low power high-Z mode. If TCLK is High
for more than 16 clock cycles, the pulse shaping circuit is disabled and
the transmit output pulse widths are determined by the TPOS and
TNEG duty cycles.
When pulse shaping is disabled, it is possible to overheat and damage
the LXT384 device by leaving transmit inputs high continuously. For
example a programmable ASIC might leave all outputs high until it is
programmed. To prevent this, clock one of these signals: TPOS, TNEG,
TCLK or MCLK. Another solution is to set one of these signals low:
TPOS, TNEG, TCLK, or OE.
Note:
The TAOS generator uses MCLK as a timing reference. In order
to assure that the output frequency is within specification limits,
MCLK must have the applicable stability.
3
E3
LOS6
DO
Loss of Signal Output.
LOS output is High, indicating a loss of signal,
when the incoming signal has no transitions for a specified time interval.
The LOS condition is cleared and the output pin returns to Low when
the incoming signal has sufficient number of transitions in a specified
time interval (details in LOS functional description).
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
TCLK
Operating Mode
Clocked
Normal operation
H
TAOS (if MCLK supplied)
H
Disable transmit pulse shaping (when
MCLK is not available)
L
Driver outputs enter tri-state
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT384LE | Telecomm/Datacomm |
| LXT386BE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT388LE | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT400JE | Hermetically Sealed, 3.3V, High Speed, High CMR, Logic Gate Optocoupler |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT384LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT386 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:QUAD T1/E1/J1 Transceiver |
| LXT386BE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | 制造商:LEVEL1 功能描述: |
| LXT388LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
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